From 4ce6e0538bfab2542aed399e67a1897decb2bbf6 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Thu, 6 Mar 2025 02:05:43 -0800 Subject: [PATCH] fix col_cap array for dummu compatability ...bitcells next --- Makefile | 3 +-- .../modules/capped_replica_bitcell_array.py | 8 +++++-- compiler/modules/col_cap_array.py | 2 +- compiler/modules/pattern.py | 3 --- technology/sky130/custom/sky130_col_cap.py | 21 +++++++++++++------ .../sky130/custom/sky130_col_cap_array.py | 10 +++++---- technology/sky130/tech/tech.py | 4 +++- 7 files changed, 32 insertions(+), 19 deletions(-) diff --git a/Makefile b/Makefile index ff5f5954..eb46bebf 100644 --- a/Makefile +++ b/Makefile @@ -13,8 +13,7 @@ SRAM_LIB_GIT_REPO ?= https://github.com/vlsida/sky130_fd_bd_sram.git # Use this for development #SRAM_LIB_GIT_REPO ?= git@github.com:VLSIDA/sky130_fd_bd_sram.git #SRAM_LIB_GIT_REPO ?= https://github.com/google/skywater-pdk-libs-sky130_fd_bd_sram.git -SRAM_LIB_GIT_COMMIT ?= 8dccd8d8ddb0a9de1b02207b2cd0c0d697807aa9 - +SRAM_LIB_GIT_COMMIT ?= 9bb620d12ae380dfe38f9a68df809f068f7b2a21 SKY130_PDK ?= $(PDK_ROOT)/sky130A GF180_PDK ?= $(PDK_ROOT)/gf180mcuD diff --git a/compiler/modules/capped_replica_bitcell_array.py b/compiler/modules/capped_replica_bitcell_array.py index def6251f..8832bc2f 100644 --- a/compiler/modules/capped_replica_bitcell_array.py +++ b/compiler/modules/capped_replica_bitcell_array.py @@ -87,7 +87,9 @@ class capped_replica_bitcell_array(bitcell_base_array): # dummy column + left replica column(s) column_offset=0, mirror=0, - location="top") + location="top", + left_rbl=self.left_rbl, + right_rbl=self.right_rbl) self.col_cap_bottom = factory.create(module_type=col_cap_module_type, cols=self.column_size + len(self.rbls), @@ -95,7 +97,9 @@ class capped_replica_bitcell_array(bitcell_base_array): # dummy column + left replica column(s) column_offset=0, mirror=0, - location="bottom") + location="bottom", + left_rbl=self.left_rbl, + right_rbl=self.right_rbl) # Dummy Col or Row Cap, depending on bitcell array properties row_cap_module_type = ("row_cap_array" if self.cell.end_caps else "dummy_array") diff --git a/compiler/modules/col_cap_array.py b/compiler/modules/col_cap_array.py index bc9edc3c..bf0198fc 100644 --- a/compiler/modules/col_cap_array.py +++ b/compiler/modules/col_cap_array.py @@ -12,7 +12,7 @@ class col_cap_array(bitcell_base_array): """ Generate a dummy row/column for the replica array. """ - def __init__(self, rows, cols, column_offset=0, mirror=0, location="", name=""): + def __init__(self, rows, cols, column_offset=0, mirror=0, location="", name="",left_rbl=[],right_rbl=[]): super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name) self.mirror = mirror self.location = location diff --git a/compiler/modules/pattern.py b/compiler/modules/pattern.py index abc8e931..df9ddfb8 100644 --- a/compiler/modules/pattern.py +++ b/compiler/modules/pattern.py @@ -176,9 +176,6 @@ class pattern(): self.parent_design.all_inst[row, col] = self.parent_design.add_existing_inst(inst,self.name_template.format(row, col)) self.parent_design.connect_inst(self.parent_design.get_strap_pins(self.bit_rows[col], self.bit_cols[row])) - def print_bit_blocck(): - return - def place_inst(self, inst, offset) -> None: x = offset[0] y = offset[1] diff --git a/technology/sky130/custom/sky130_col_cap.py b/technology/sky130/custom/sky130_col_cap.py index 032169ee..c03f35c3 100644 --- a/technology/sky130/custom/sky130_col_cap.py +++ b/technology/sky130/custom/sky130_col_cap.py @@ -8,20 +8,29 @@ from openram import debug from openram.base import design from openram.tech import cell_properties as props - +from openram import OPTS class sky130_col_cap(design): - def __init__(self, version, name=""): + def __init__(self, version, name="",left_rbl=[],right_rbl=[]): + if version == "colend": - cell_name = "sky130_fd_bd_sram__sram_sp_colend" + if OPTS.control_logic == "control_logic_delay" or not right_rbl: + cell_name = "sky130_fd_bd_sram__sram_sp_colend" + else: + cell_name = "sky130_fd_bd_sram__openram_sp_colend_replica" prop = props.col_cap_1port_bitcell + + elif version == "colenda": + if OPTS.control_logic == "control_logic_delay" or not left_rbl: + cell_name = "sky130_fd_bd_sram__sram_sp_colenda" + else: + cell_name = "sky130_fd_bd_sram__openram_sp_colenda_replica" + prop = props.col_cap_1port_bitcell + elif version == "colend_p_cent": cell_name = "sky130_fd_bd_sram__sram_sp_colend_p_cent" prop = props.col_cap_1port_strap_ground - elif version == "colenda": - cell_name = "sky130_fd_bd_sram__sram_sp_colenda" - prop = props.col_cap_1port_bitcell elif version == "colenda_p_cent": cell_name = "sky130_fd_bd_sram__sram_sp_colenda_p_cent" prop = props.col_cap_1port_strap_ground diff --git a/technology/sky130/custom/sky130_col_cap_array.py b/technology/sky130/custom/sky130_col_cap_array.py index 960a87be..5e376f19 100644 --- a/technology/sky130/custom/sky130_col_cap_array.py +++ b/technology/sky130/custom/sky130_col_cap_array.py @@ -18,18 +18,20 @@ class sky130_col_cap_array(col_cap_array, sky130_bitcell_base_array): """ Generate a dummy row/column for the replica array. """ - def __init__(self, rows, cols, column_offset=0, mirror=0, location="", name=""): - super().__init__(rows, cols, column_offset=column_offset, mirror=mirror, location=location, name=name) + def __init__(self, rows, cols, column_offset=0, mirror=0, location="", name="", left_rbl=[],right_rbl=[]): + self.left_rbl = left_rbl + self.right_rbl = right_rbl + super().__init__(rows, cols, column_offset=column_offset, mirror=mirror, location=location, name=name, left_rbl=left_rbl, right_rbl=right_rbl) self.no_instances = False def add_modules(self): """ Add the modules used in this design """ if self.location == "top": - self.colend1 = factory.create(module_type="col_cap", version="colend") + self.colend1 = factory.create(module_type="col_cap", version="colend",left_rbl=self.left_rbl, right_rbl=self.right_rbl) self.colend2 = factory.create(module_type="col_cap", version="colend_p_cent") self.colend3 = factory.create(module_type="col_cap", version="colend_cent") elif self.location == "bottom": - self.colend1 = factory.create(module_type="col_cap", version="colenda") + self.colend1 = factory.create(module_type="col_cap", version="colenda",left_rbl=self.left_rbl, right_rbl=self.right_rbl) self.colend2 = factory.create(module_type="col_cap", version="colenda_p_cent") self.colend3 = factory.create(module_type="col_cap", version="colenda_cent") diff --git a/technology/sky130/tech/tech.py b/technology/sky130/tech/tech.py index 0d23da8a..fe2be437 100755 --- a/technology/sky130/tech/tech.py +++ b/technology/sky130/tech/tech.py @@ -814,7 +814,9 @@ flatglob = ["*_?mos_m*", blackbox_cells = ["sky130_fd_bd_sram__openram_dp_cell", "sky130_fd_bd_sram__openram_dp_cell_dummy", "sky130_fd_bd_sram__openram_dp_cell_replica", - + + "sky130_fd_bd_sram__openram_sp_colend_replica", + "sky130_fd_bd_sram__openram_sp_colenda_replica", "sky130_fd_bd_sram__sram_sp_cell_opt1a", "sky130_fd_bd_sram__openram_sp_cell_opt1a_dummy", "sky130_fd_bd_sram__openram_sp_cell_opt1_dummy",