mirror of https://github.com/VLSIDA/OpenRAM.git
98 lines
4.4 KiB
Python
98 lines
4.4 KiB
Python
#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California
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# All rights reserved.
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#
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from openram.base import geometry
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from openram.sram_factory import factory
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from openram.tech import layer
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from openram import OPTS
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from openram.modules.col_cap_array import col_cap_array
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from .sky130_bitcell_base_array import sky130_bitcell_base_array
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from openram.modules import pattern
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from math import ceil
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class sky130_col_cap_array(col_cap_array, sky130_bitcell_base_array):
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"""
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Generate a dummy row/column for the replica array.
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"""
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def __init__(self, rows, cols, column_offset=0, mirror=0, location="", name="", left_rbl=[],right_rbl=[]):
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self.left_rbl = left_rbl
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self.right_rbl = right_rbl
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super().__init__(rows, cols, column_offset=column_offset, mirror=mirror, location=location, name=name, left_rbl=left_rbl, right_rbl=right_rbl)
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self.no_instances = False
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def add_modules(self):
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""" Add the modules used in this design """
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if self.location == "top":
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self.colend1 = factory.create(module_type="col_cap", version="colend",left_rbl=self.left_rbl, right_rbl=self.right_rbl)
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self.colend2 = factory.create(module_type="col_cap", version="colend_p_cent")
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self.colend3 = factory.create(module_type="col_cap", version="colend_cent")
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elif self.location == "bottom":
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self.colend1 = factory.create(module_type="col_cap", version="colenda",left_rbl=self.left_rbl, right_rbl=self.right_rbl)
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self.colend2 = factory.create(module_type="col_cap", version="colenda_p_cent")
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self.colend3 = factory.create(module_type="col_cap", version="colenda_cent")
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self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
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def create_instances(self):
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self.all_inst={}
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self.cell_inst={}
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if self.location == "top":
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bit_row = [geometry.instance("00_colend", mod=self.colend1, is_bitcell=True)] \
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+ [geometry.instance("01_strap_p_cent", mod=self.colend2, is_bitcell=False)]\
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+ [geometry.instance("02_colend", mod=self.colend1, is_bitcell=True, mirror="MY")] \
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+ [geometry.instance("03_strap_p", mod=self.colend3, is_bitcell=False)]
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elif self.location == "bottom":
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bit_row = [geometry.instance("00_colend", mod=self.colend1, is_bitcell=True, mirror="MX")] \
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+ [geometry.instance("01_strap_p_cent", mod=self.colend2, is_bitcell=False, mirror="MX")]\
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+ [geometry.instance("02_colend", mod=self.colend1, is_bitcell=True, mirror="XY")] \
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+ [geometry.instance("03_strap_p", mod=self.colend3, is_bitcell=False, mirror="MX")]
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bit_row = pattern.rotate_list(bit_row, self.column_offset * 2)
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bit_block = []
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pattern.append_row_to_block(bit_block, bit_row)
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self.pattern = pattern(self, "col_cap_array_" + self.location , bit_block, num_rows=self.row_size, num_cols=self.column_size, num_cores_x=ceil(self.column_size/2), num_cores_y=ceil(self.row_size/2), name_template="col_cap_array" + self.location + "_r{0}_c{1}")
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self.pattern.connect_array()
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def get_bitcell_pins(self, row, col):
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"""
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Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array
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"""
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bitcell_pins = []
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for port in self.all_ports:
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bitcell_pins.extend([x for x in self.get_bitline_names(port) if x.endswith("_{0}".format(col))])
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bitcell_pins.append("vdd") # vdd
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bitcell_pins.append("gnd") # gnd
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bitcell_pins.append("vdd") # vpb
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bitcell_pins.append("gnd") # vnb
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bitcell_pins.append("gnd")# poly gate for parasitic tx
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#bitcell_pins.extend([x for x in self.all_wordline_names if x.endswith("_{0}".format(row))])
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return bitcell_pins
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def get_strap_pins(self, row, col):
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strap_pins = []
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if col % 2 == 0 and col % 4 != 0:
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strap_pins.append("vdd") # vdd
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else:
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strap_pins.append("gnd") # gnd
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strap_pins.append("vdd") # vpb
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strap_pins.append("gnd") # vnb
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return strap_pins
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def create_layout(self):
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self.place_array()
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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