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Added optional write_size and wmask.

This commit is contained in:
jsowash 2019-07-03 10:14:15 -07:00
parent 67c6cdf3bb
commit 474ac67af5
2 changed files with 5 additions and 1 deletions
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3
compiler/characterizer/simulation.py
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@ -24,6 +24,7 @@ class simulation():
self.name = self.sram.name self.name = self.sram.name
self.word_size = self.sram.word_size self.word_size = self.sram.word_size
self.addr_size = self.sram.addr_size self.addr_size = self.sram.addr_size
self.write_size = self.sram.write_size
self.num_cols = self.sram.num_cols self.num_cols = self.sram.num_cols
self.num_rows = self.sram.num_rows self.num_rows = self.sram.num_rows
self.num_banks = self.sram.num_banks self.num_banks = self.sram.num_banks
@ -266,6 +267,8 @@ class simulation():
for port in range(total_ports): for port in range(total_ports):
if (port in read_index) and (port in write_index): if (port in read_index) and (port in write_index):
pin_names.append("WEB{0}".format(port)) pin_names.append("WEB{0}".format(port))
if (self.write_size != self.word_size):
pin_names.append("WMASK{0}".format(port))
for port in range(total_ports): for port in range(total_ports):
pin_names.append("{0}{1}".format(tech.spice["clk"], port)) pin_names.append("{0}{1}".format(tech.spice["clk"], port))

1
compiler/modules/control_logic.py
View File

@ -75,6 +75,7 @@ class control_logic(design.design):
def add_pins(self): def add_pins(self):
""" Add the pins to the control logic module. """ """ Add the pins to the control logic module. """
for pin in self.input_list + ["clk"]: for pin in self.input_list + ["clk"]:
print(pin)
self.add_pin(pin,"INPUT") self.add_pin(pin,"INPUT")
for pin in self.output_list: for pin in self.output_list:
self.add_pin(pin,"OUTPUT") self.add_pin(pin,"OUTPUT")