From 474ac67af5bcd910217e603fe9aec503a43c9061 Mon Sep 17 00:00:00 2001 From: jsowash Date: Wed, 3 Jul 2019 10:14:15 -0700 Subject: [PATCH] Added optional write_size and wmask. --- compiler/characterizer/simulation.py | 5 ++++- compiler/modules/control_logic.py | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index 83d367b0..c5e26da1 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -24,6 +24,7 @@ class simulation(): self.name = self.sram.name self.word_size = self.sram.word_size self.addr_size = self.sram.addr_size + self.write_size = self.sram.write_size self.num_cols = self.sram.num_cols self.num_rows = self.sram.num_rows self.num_banks = self.sram.num_banks @@ -266,7 +267,9 @@ class simulation(): for port in range(total_ports): if (port in read_index) and (port in write_index): pin_names.append("WEB{0}".format(port)) - + if (self.write_size != self.word_size): + pin_names.append("WMASK{0}".format(port)) + for port in range(total_ports): pin_names.append("{0}{1}".format(tech.spice["clk"], port)) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 7b863b7a..fa269e26 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -75,6 +75,7 @@ class control_logic(design.design): def add_pins(self): """ Add the pins to the control logic module. """ for pin in self.input_list + ["clk"]: + print(pin) self.add_pin(pin,"INPUT") for pin in self.output_list: self.add_pin(pin,"OUTPUT")