Use array ur instead of bank ur to pace row addr dff

2026-08-29 01:24:39 +02:00 · 2018-11-19 08:41:26 -08:00
parent 7709d5caa7
commit 4630f52de2
3 changed files with 11 additions and 10 deletions
@@ -65,8 +65,7 @@ class bank(design.design):
        self.bank_array_ur = self.bitcell_array_inst.ur()
        
        self.DRC_LVS()
- 
- 
+
    def add_pins(self):
        """ Adding pins for Bank module"""
        for port in self.read_ports: