From 4630f52de2ffede1f5a2fba2f76a2280174b8135 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 19 Nov 2018 08:41:26 -0800 Subject: [PATCH] Use array ur instead of bank ur to pace row addr dff --- README.md | 4 ++-- compiler/modules/bank.py | 3 +-- compiler/sram_1bank.py | 14 ++++++++------ 3 files changed, 11 insertions(+), 10 deletions(-) diff --git a/README.md b/README.md index 03b7213f..91e00bbd 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,6 @@ # OpenRAM -Stable: [![pipeline status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/master) -Unstable: [![pipeline status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/dev) +Master: [![pipeline status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/master) +Dev: [![pipeline status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/dev) [![Download](images/download.svg)](https://github.com/VLSIDA/PrivateRAM/archive/master.zip) [![License: BSD 3-clause](./images/license_badge.svg)](./LICENSE) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 8014b81c..c4f4d557 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -65,8 +65,7 @@ class bank(design.design): self.bank_array_ur = self.bitcell_array_inst.ur() self.DRC_LVS() - - + def add_pins(self): """ Adding pins for Bank module""" for port in self.read_ports: diff --git a/compiler/sram_1bank.py b/compiler/sram_1bank.py index 896dcf6b..49ad4f9b 100644 --- a/compiler/sram_1bank.py +++ b/compiler/sram_1bank.py @@ -73,9 +73,10 @@ class sram_1bank(sram_base): self.control_logic_insts[port].place(control_pos[port]) # The row address bits are placed above the control logic aligned on the right. - # Or just below the top of the bank, whichever is greater. - row_addr_pos[port] = vector(self.control_logic_insts[port].rx() - self.row_addr_dff_insts[port].width, - max(self.control_logic_insts[port].uy(), self.bank_inst.ul().y - self.row_addr_dff_insts[port].height)) + x_offset = self.control_logic_insts[port].rx() - self.row_addr_dff_insts[port].width + # It is aove the control logic but below the top of the bitcell array + y_offset = max(self.control_logic_insts[port].uy(), self.bank.bank_array_ur.y - self.row_addr_dff_insts[port].height) + row_addr_pos[port] = vector(x_offset, y_offset) self.row_addr_dff_insts[port].place(row_addr_pos[port]) # Add the col address flops below the bank to the left of the lower-left of bank array @@ -104,9 +105,10 @@ class sram_1bank(sram_base): self.control_logic_insts[port].place(control_pos[port], mirror="MY") # The row address bits are placed above the control logic aligned on the left. - # Or just below the top of the bank, whichever is greater. - row_addr_pos[port] = vector(control_pos[port].x - self.control_logic_insts[port].width + self.row_addr_dff_insts[port].width, - max(self.control_logic_insts[port].uy(), self.bank_inst.ul().y - self.row_addr_dff_insts[port].height)) + x_offset = control_pos[port].x - self.control_logic_insts[port].width + self.row_addr_dff_insts[port].width + # It is above the control logic but below the top of the bitcell array + y_offset = max(self.control_logic_insts[port].uy(), self.bank.bank_array_ur.y - self.row_addr_dff_insts[port].height) + row_addr_pos[port] = vector(x_offset, y_offset) self.row_addr_dff_insts[port].place(row_addr_pos[port], mirror="MY") # Add the col address flops above the bank to the right of the upper-right of bank array