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Rotate via in center for freepdk

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This commit is contained in:
Matt Guthaus
2018-07-19 14:01:48 -07:00
parent 4c3bd0e42b
commit 45a53ed089
2 changed files with 9 additions and 6 deletions
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compiler/modules/replica_bitline.py
+6 -3
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@@ -169,9 +169,12 @@ class replica_bitline(design.design):
self.add_power_pin("vdd", pin.lc())
# Replica bitcell needs to be routed up to M3
for pin_name in ["vdd", "gnd"]:
for pin in self.rbc_inst.get_pins(pin_name):
self.add_power_pin(pin_name, pin.center())
pin=self.rbc_inst.get_pin("vdd")
# Don't rotate this via to vit in FreePDK45
self.add_power_pin("vdd", pin.center(), False)
for pin in self.rbc_inst.get_pins("gnd"):
self.add_power_pin("gnd", pin.center())