diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py
index 43fb22d2..80034591 100644
--- a/compiler/base/hierarchy_layout.py
+++ b/compiler/base/hierarchy_layout.py
@@ -654,16 +654,16 @@ class layout(lef.lef):
                       width=xmax-xmin,
                       height=ymax-ymin)
 
-    def add_power_pin(self, name, loc):
+    def add_power_pin(self, name, loc, rotate=True):
         """ 
         Add a single power pin from M3 own to M1
         """
         self.add_via_center(layers=("metal1", "via1", "metal2"),
                             offset=loc,
-                            rotate=90)
+                            rotate=90 if rotate else 0)
         self.add_via_center(layers=("metal2", "via2", "metal3"),
                             offset=loc,
-                            rotate=90)
+                            rotate=90 if rotate else 0)
         self.add_layout_pin_rect_center(text=name,
                                         layer="metal3",
                                         offset=loc)
diff --git a/compiler/modules/replica_bitline.py b/compiler/modules/replica_bitline.py
index 79d905bf..bf6b8f92 100644
--- a/compiler/modules/replica_bitline.py
+++ b/compiler/modules/replica_bitline.py
@@ -169,9 +169,12 @@ class replica_bitline(design.design):
         self.add_power_pin("vdd", pin.lc())
             
         # Replica bitcell needs to be routed up to M3
-        for pin_name in ["vdd", "gnd"]:
-            for pin in self.rbc_inst.get_pins(pin_name):
-                self.add_power_pin(pin_name, pin.center())
+        pin=self.rbc_inst.get_pin("vdd")
+        # Don't rotate this via to vit in FreePDK45
+        self.add_power_pin("vdd", pin.center(), False)
+        
+        for pin in self.rbc_inst.get_pins("gnd"):
+            self.add_power_pin("gnd", pin.center())