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use cs_buf for sense amp on r ports instead of cs

This commit is contained in:
samuelkcrow 2022-05-04 12:51:31 -07:00
parent c4138c9f9b
commit 45239ca2a9
1 changed files with 1 additions and 1 deletions
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2
compiler/modules/control_logic_delay.py
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@ -617,7 +617,7 @@ class control_logic_delay(design.design):
if self.port_type=="rw": if self.port_type=="rw":
input_name = "we_bar" input_name = "we_bar"
else: else:
input_name = "cs" input_name = "cs_buf"
# GATE FOR S_EN # GATE FOR S_EN
self.s_en_gate_inst = self.add_inst(name="and_s_en", self.s_en_gate_inst = self.add_inst(name="and_s_en",
mod=self.sen_and3) mod=self.sen_and3)