From 45239ca2a9715b4167184162ea321c7e9d998f26 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Wed, 4 May 2022 12:51:31 -0700 Subject: [PATCH] use cs_buf for sense amp on r ports instead of cs --- compiler/modules/control_logic_delay.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index 00038758..c6dbd5bd 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -617,7 +617,7 @@ class control_logic_delay(design.design): if self.port_type=="rw": input_name = "we_bar" else: - input_name = "cs" + input_name = "cs_buf" # GATE FOR S_EN self.s_en_gate_inst = self.add_inst(name="and_s_en", mod=self.sen_and3)