From 450f8ab0c360d8d04a7060d5128d6b31578d4361 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Tue, 22 Aug 2023 00:45:57 -0700 Subject: [PATCH] replica col generating, funny dummy cell placement --- compiler/modules/pattern.py | 30 ++- compiler/modules/replica_column.py | 6 - .../sky130/custom/sky130_replica_column.py | 226 ++++-------------- 3 files changed, 72 insertions(+), 190 deletions(-) diff --git a/compiler/modules/pattern.py b/compiler/modules/pattern.py index 8b6070db..a7cc062f 100644 --- a/compiler/modules/pattern.py +++ b/compiler/modules/pattern.py @@ -36,7 +36,7 @@ class pattern(): initial_x_block:bool = False, initial_y_block:bool = False, final_x_block:bool = False, - final_y_block:bool = False + final_y_block:bool = False, ): """ a "block" is a 2d list of instances @@ -72,6 +72,9 @@ class pattern(): self.final_y_block = final_y_block self.bits_per_row = ceil(self.num_rows/self.num_cores_x) self.bits_per_col = ceil(self.num_cols/self.num_cores_y) + self.bit_rows = [] + self.bit_cols = [] + self.parent_design.all_inst = {} if not OPTS.netlist_only: self.verify_interblock_dimensions() @@ -130,8 +133,6 @@ class pattern(): continue if((self.bit_rows[col+dc] < self.num_rows) and (self.bit_cols[row+dr] < self.num_cols)): if(inst.is_bitcell): - #x_bit = sum(bit > 0 for bit in self.bit_rows) - #y_bit = sum(bit > 0 for bit in self.bit_cols) #print(x_bit, y_bit) self.parent_design.cell_inst[self.bit_rows[col+dc], self.bit_cols[row+dr]] = self.parent_design.add_existing_inst(inst,self.name_template.format(row +dr, col+dc)) self.parent_design.all_inst[row + dr, col + dc] = self.parent_design.cell_inst[self.bit_rows[col+dc], self.bit_cols[row+dr]] @@ -146,8 +147,7 @@ class pattern(): row_done = True def connect_array(self) -> None: - self.bit_rows = [] - self.bit_cols = [] + #debug_array = [[None]*12 for _ in range(6)] row = 0 col = 0 @@ -157,6 +157,26 @@ class pattern(): col += len(self.core_block[0]) col = 0 row += len(self.core_block) + + def connect_array_raw(self) -> None: + for row in range(self.num_rows): + for col in range(self.num_cols): + inst = self.core_block[row][col] + if(len(self.bit_rows) <= col): + self.bit_rows.append(0) + if(len(self.bit_cols) <= row): + self.bit_cols.append(0) + if(inst.is_bitcell): + self.parent_design.cell_inst[self.bit_rows[col], self.bit_cols[row]] = self.parent_design.add_existing_inst(inst,self.name_template.format(row, col)) + self.parent_design.all_inst[row, col] = self.parent_design.cell_inst[self.bit_rows[col], self.bit_cols[row]] + self.parent_design.connect_inst(self.parent_design.get_bitcell_pins(self.bit_rows[col], self.bit_cols[row])) + self.bit_rows[col] += 1 + self.bit_cols[row] += 1 + + else: + self.parent_design.all_inst[row, col] = self.parent_design.add_existing_inst(inst,self.name_template.format(row, col)) + self.parent_design.connect_inst(self.parent_design.get_strap_pins(self.bit_rows[col], self.bit_cols[row])) + def place_inst(self, inst, offset) -> None: x = offset[0] diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index c6cdd492..dc1b6f12 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -132,12 +132,6 @@ class replica_column(bitcell_base_array): width=self.width, height=wl_pin.height()) - def route_supplies(self): - - for inst in self.cell_inst.values(): - for pin_name in ["vdd", "gnd"]: - self.copy_layout_pin(inst, pin_name) - def get_bitline_names(self, port=None): if port == None: return self.all_bitline_names diff --git a/technology/sky130/custom/sky130_replica_column.py b/technology/sky130/custom/sky130_replica_column.py index 4d95a3a4..9eca5dfd 100644 --- a/technology/sky130/custom/sky130_replica_column.py +++ b/technology/sky130/custom/sky130_replica_column.py @@ -11,7 +11,7 @@ from openram.sram_factory import factory from openram.tech import layer from openram import OPTS from .sky130_bitcell_base_array import sky130_bitcell_base_array - +from openram.modules import pattern class sky130_replica_column(sky130_bitcell_base_array): """ @@ -31,8 +31,6 @@ class sky130_replica_column(sky130_bitcell_base_array): self.row_start = rbl[0] + 1 # End of regular word line rows self.row_end = self.row_start + rows - if not self.cell.end_caps: - self.row_size += 2 super().__init__(rows=self.row_size, cols=1, column_offset=column_offset, name=name) self.rows = rows @@ -41,23 +39,17 @@ class sky130_replica_column(sky130_bitcell_base_array): self.replica_bit = replica_bit # left, right, regular rows plus top/bottom dummy cells - self.total_size = self.left_rbl + rows + self.right_rbl + 2 + self.total_size = self.left_rbl + rows + self.right_rbl self.column_offset = column_offset - if self.rows % 2 == 0: - debug.error("Invalid number of rows {}. Number of rows must be even to connect to col ends".format(self.rows), -1) - if self.column_offset % 2 == 0: - debug.error("Invalid column_offset {}. Column offset must be odd to connect to col ends".format(self.rows), -1) - debug.check(replica_bit != 0 and replica_bit != rows, - "Replica bit cannot be the dummy row.") - debug.check(replica_bit <= self.left_rbl or replica_bit >= self.total_size - self.right_rbl - 1, - "Replica bit cannot be in the regular array.") - # if OPTS.tech_name == "sky130": - # debug.check(rows % 2 == 0 and (self.left_rbl + 1) % 2 == 0, - # "sky130 currently requires rows to be even and to start with X mirroring" - # + " (left_rbl must be even) for LVS.") - # commented out to support odd row counts while testing opc - + # if self.rows % 2 == 0: + # debug.error("Invalid number of rows {}. Number of rows must be even to connect to col ends".format(self.rows), -1) + # if self.column_offset % 2 == 0: + # debug.error("Invalid column_offset {}. Column offset must be odd to connect to col ends".format(self.rows), -1) + # debug.check(replica_bit != 0 and replica_bit != rows, + # "Replica bit cannot be the dummy row.") + # debug.check(replica_bit <= self.left_rbl or replica_bit >= self.total_size - self.right_rbl - 1, + # "Replica bit cannot be in the regular array.") self.create_netlist() if not OPTS.netlist_only: self.create_layout() @@ -68,10 +60,7 @@ class sky130_replica_column(sky130_bitcell_base_array): self.create_instances() def create_layout(self): - self.place_instances() - - self.width = max([x.rx() for x in self.insts]) - self.height = max([x.uy() for x in self.insts]) + self.place_array() self.add_layout_pins() @@ -83,15 +72,15 @@ class sky130_replica_column(sky130_bitcell_base_array): self.create_all_bitline_names() #self.create_all_wordline_names(self.row_size+2) # +2 to add fake wl pins for colends - self.create_all_wordline_names(self.row_size+1, 1) + self.create_all_wordline_names(self.row_size) self.add_pin_list(self.all_bitline_names, "OUTPUT") self.add_pin_list(self.all_wordline_names, "INPUT") self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") - self.add_pin("top_gate", "INPUT") - self.add_pin("bot_gate", "INPUT") + #self.add_pin("top_gate", "INPUT") + #self.add_pin("bot_gate", "INPUT") def add_modules(self): self.replica_cell = factory.create(module_type="replica_bitcell_1port", version="opt1") @@ -101,165 +90,44 @@ class sky130_replica_column(sky130_bitcell_base_array): self.dummy_cell = factory.create(module_type="dummy_bitcell_1port", version="opt1") self.dummy_cell2 = factory.create(module_type="dummy_bitcell_1port", version="opt1") - self.strap1 = factory.create(module_type="internal", version="wlstrap") - self.strap2 = factory.create(module_type="internal", version="wlstrap_p") - self.strap3 = factory.create(module_type="internal", version="wlstrapa_p") - - self.colend = factory.create(module_type="col_cap", version="colend") - self.edge_cell = self.colend - self.colenda = factory.create(module_type="col_cap", version="colenda") - self.colend_p_cent = factory.create(module_type="col_cap", version="colend_p_cent") - self.colenda_p_cent = factory.create(module_type="col_cap", version="colenda_p_cent") + self.strap = factory.create(module_type="internal", version="wlstrap_p") + self.strap2 = factory.create(module_type="internal", version="wlstrapa_p") def create_instances(self): - self.cell_inst = {} - self.array_layout = [] - alternate_bitcell = (self.rows + 1) % 2 + """ Create the module instances used in this design """ + self.all_inst={} + self.cell_inst={} + replica_row_opt1 = [geometry.instance("00_rep_opt1", mod=self.replica_cell, is_bitcell=True, mirror='MX')] \ + + [geometry.instance("01_strap1", mod=self.strap, is_bitcell=False, mirror='MX')] + + replica_row_opt1a = [geometry.instance("10_opt1a", mod=self.replica_cell2, is_bitcell=True)] \ + + [geometry.instance("11_strapa", mod=self.strap2, is_bitcell=False)] + + replica_dummy_row_opt1 = [geometry.instance("00_rep_opt1", mod=self.dummy_cell, is_bitcell=True, mirror='MX')] \ + + [geometry.instance("01_rep_strap", mod=self.strap, is_bitcell=False, mirror='MX')] + + replica_dummy_row_opt1a = [geometry.instance("10_opt1a", mod=self.dummy_cell2, is_bitcell=True)] \ + + [geometry.instance("11_strapa", mod=self.strap2, is_bitcell=False)] + + bit_block = [] + current_row = self.row_start for row in range(self.total_size): - row_layout = [] - name="rbc_{0}".format(row) - # Top/bottom cell are always dummy cells. - # Regular array cells are replica cells (>left_rbl and self.left_rbl and row < self.total_size - 1 or row == self.replica_bit): - - if alternate_bitcell == 0: - row_layout.append(self.replica_cell) - self.cell_inst[row]=self.add_inst(name=name, mod=self.replica_cell) - self.connect_inst(self.get_bitcell_pins(row, 0)) - row_layout.append(self.strap2) - self.add_inst(name=name + "_strap_p", mod=self.strap2) - self.connect_inst(self.get_strap_pins(row, 0, name + "_strap_p")) - alternate_bitcell = 1 - + # Regular array cells are replica cells + # Replic bit specifies which other bit (in the full range (0,total_size) to make a replica cell. + # All other cells are dummies + if (row == self.replica_bit) or (row >= self.row_start and row < self.row_end): + if current_row % 2: + pattern.append_row_to_block(bit_block, replica_row_opt1) else: - row_layout.append(self.replica_cell2) - self.cell_inst[row]=self.add_inst(name=name, mod=self.replica_cell2) - self.connect_inst(self.get_bitcell_pins(row, 0)) - row_layout.append(self.strap3) - self.add_inst(name=name + "_strap", mod=self.strap3) - self.connect_inst(self.get_strap_pins(row, 0)) - alternate_bitcell = 0 - - elif (row == 0): - row_layout.append(self.colend) - self.cell_inst[row]=self.add_inst(name=name, mod=self.colend) - self.connect_inst(self.get_col_cap_pins(row, 0)) - row_layout.append(self.colend_p_cent) - self.add_inst(name=name + "_cap", mod=self.colend_p_cent) - self.connect_inst(self.get_col_cap_p_pins(row, 0)) - elif (row == self.total_size - 1): - row_layout.append(self.colenda) - self.cell_inst[row]=self.add_inst(name=name, mod=self.colenda) - self.connect_inst(self.get_col_cap_pins(row, 0)) - row_layout.append(self.colenda_p_cent) - self.add_inst(name=name + "_cap", mod=self.colenda_p_cent) - self.connect_inst(self.get_col_cap_p_pins(row, 0)) - - self.array_layout.append(row_layout) - - def place_instances(self, name_template="", row_offset=0): - col_offset = self.column_offset - yoffset = 0.0 - - for row in range(row_offset, len(self.array_layout) + row_offset): - xoffset = 0.0 - for col in range(col_offset, len(self.array_layout[row]) + col_offset): - self.place_inst = self.insts[(col - col_offset) + (row - row_offset) * len(self.array_layout[row - row_offset])] - if row == row_offset or row == (len(self.array_layout) + row_offset -1): - if row == row_offset: - self.place_inst.place(offset=[xoffset, yoffset + self.colend.height], mirror="MX") - else: - self.place_inst.place(offset=[xoffset, yoffset]) - - elif col % 2 == 0: - if row % 2 == 0: - self.place_inst.place(offset=[xoffset, yoffset + self.place_inst.height], mirror="MX") - else: - self.place_inst.place(offset=[xoffset, yoffset]) - else: - if row % 2 == 0: - self.place_inst.place(offset=[xoffset + self.place_inst.width, yoffset + self.place_inst.height], mirror="XY") - else: - self.place_inst.place(offset=[xoffset + self.place_inst.width, yoffset], mirror="MY") - - xoffset += self.place_inst.width - if row == row_offset: - yoffset += self.colend.height + pattern.append_row_to_block(bit_block, replica_row_opt1a) else: - yoffset += self.place_inst.height - - self.width = max([x.rx() for x in self.insts]) - self.height = max([x.uy() for x in self.insts]) - - def add_layout_pins(self): - """ Add the layout pins """ - for port in self.all_ports: - bl_pin = self.cell_inst[2].get_pin(self.cell.get_bl_name(port)) - self.add_layout_pin(text="bl_{0}_{1}".format(port, 0), - layer=bl_pin.layer, - offset=bl_pin.ll().scale(1, 0), - width=bl_pin.width(), - height=self.height) - bl_pin = self.cell_inst[2].get_pin(self.cell.get_br_name(port)) - self.add_layout_pin(text="br_{0}_{1}".format(port, 0), - layer=bl_pin.layer, - offset=bl_pin.ll().scale(1, 0), - width=bl_pin.width(), - height=self.height) - - row_range_max = self.total_size - 1 - row_range_min = 1 - - for port in self.all_ports: - for row in range(row_range_min, row_range_max): - wl_pin = self.cell_inst[row].get_pin(self.cell.get_wl_name(port)) - self.add_layout_pin(text="wl_{0}_{1}".format(port, row_range_max-row), - layer=wl_pin.layer, - offset=wl_pin.ll().scale(0, 1), - width=self.width, - height=wl_pin.height()) - - # for colend in [self.cell_inst[0], self.cell_inst[self.row_size]]: - # inst = self.cell_inst[row] - # for pin_name in ["top_gate", "bot_gate"]: - # pin = inst.get_pin("gate") - # self.add_layout_pin(text=pin_name, - # layer=pin.layer, - # offset=pin.ll(), - # width=pin.width(), - # height=pin.height()) - - for row in range(self.row_size + 2): - inst = self.cell_inst[row] - # add only 1 label per col - for pin_name in ["vdd", "gnd"]: - self.copy_layout_pin(inst, pin_name) - #if row == 2: - if 'VPB' or 'vpb' in self.cell_inst[row].mod.pins: - pin = inst.get_pin("vpb") - self.objs.append(geometry.rectangle(layer["nwell"], - pin.ll(), - pin.width(), - pin.height())) - self.objs.append(geometry.label("vdd", layer["nwell"], pin.center())) - - if 'VNB' or 'vnb' in self.cell_inst[row].mod.pins: - try: - from openram.tech import layer_override - if layer_override['VNB']: - pin = inst.get_pin("vnb") - self.add_label("gnd", pin.layer, pin.center()) - self.objs.append(geometry.rectangle(layer["pwellp"], - pin.ll(), - pin.width(), - pin.height())) - self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center())) - - - except: - pin = inst.get_pin("vnb") - self.add_label("gnd", pin.layer, pin.center()) + if current_row %2: + pattern.append_row_to_block(bit_block, replica_dummy_row_opt1) + else: + pattern.append_row_to_block(bit_block, replica_dummy_row_opt1a) + current_row += 1 + self.pattern = pattern(self, "replica_column", bit_block, num_rows=self.total_size, num_cols=len(replica_row_opt1a), name_template="rbc_r{0}_c{1}", ) + self.pattern.connect_array_raw() def exclude_all_but_replica(self): """