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Change s8 to sky130

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This commit is contained in:
mrg
2020-06-12 14:23:26 -07:00
parent 54e4d147f6
commit 443b8fbe23
21 changed files with 39 additions and 36 deletions
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compiler/modules/bitcell_base_array.py
+1 -1
View File
@@ -102,7 +102,7 @@ class bitcell_base_array(design.design):
height=wl_pin.height())
# For non-square via stacks, vertical/horizontal direction refers to the stack orientation in 2d space
# Default uses prefered directions for each layer; this cell property is only currently used by s8 tech (03/20)
# Default uses prefered directions for each layer; this cell property is only currently used by sky130 tech (03/20)
try:
bitcell_power_pin_directions = cell_properties.bitcell_power_pin_directions
except AttributeError:
compiler/modules/hierarchical_decoder.py
+2 -2
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@@ -159,7 +159,7 @@ class hierarchical_decoder(design.design):
# Inputs to cells are on input layer
# Outputs from cells are on output layer
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
self.bus_layer = "m1"
self.bus_directions = "nonpref"
self.bus_pitch = self.m1_pitch
@@ -525,7 +525,7 @@ class hierarchical_decoder(design.design):
must-connects next level up.
"""
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
for n in ["vdd", "gnd"]:
pins = self.and_inst[0].get_pins(n)
for pin in pins:
compiler/modules/hierarchical_predecode.py
+4 -4
View File
@@ -78,7 +78,7 @@ class hierarchical_predecode(design.design):
# Inputs to cells are on input layer
# Outputs from cells are on output layer
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
self.bus_layer = "m1"
self.bus_directions = None
self.bus_pitch = self.m1_pitch
@@ -239,7 +239,7 @@ class hierarchical_predecode(design.design):
# add output so that it is just below the vdd or gnd rail
# since this is where the p/n devices are and there are no
# pins in the and gates.
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
rail_pos = vector(self.decode_rails[out_pin].cx(), inv_out_pos.y)
self.add_path(self.output_layer, [inv_out_pos, rail_pos])
else:
@@ -309,8 +309,8 @@ class hierarchical_predecode(design.design):
def route_vdd_gnd(self):
""" Add a pin for each row of vdd/gnd which are must-connects next level up. """
# In s8, we use hand-made decoder cells with vertical power
if OPTS.tech_name == "s8":
# In sky130, we use hand-made decoder cells with vertical power
if OPTS.tech_name == "sky130":
for n in ["vdd", "gnd"]:
# This makes a wire from top to bottom for both inv and and gates
for i in [self.inv_inst, self.and_inst]:
compiler/modules/port_data.py
+2 -2
View File
@@ -588,7 +588,7 @@ class port_data(design.design):
# This could be a channel route, but in some techs the bitlines
# are too close together.
elif OPTS.tech_name == "s8":
elif OPTS.tech_name == "sky130":
self.connect_bitlines(inst1=inst1,
inst1_bls_template=inst1_bls_templ,
inst2=inst2,
@@ -646,7 +646,7 @@ class port_data(design.design):
# This could be a channel route, but in some techs the bitlines
# are too close together.
elif OPTS.tech_name == "s8":
elif OPTS.tech_name == "sky130":
self.connect_bitlines(inst1=inst1, inst2=inst2,
num_bits=self.word_size,
inst1_bls_template=inst1_bls_templ,
compiler/modules/wordline_driver_array.py
+1 -1
View File
@@ -68,7 +68,7 @@ class wordline_driver_array(design.design):
Add a pin for each row of vdd/gnd which
are must-connects next level up.
"""
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
for name in ["vdd", "gnd"]:
supply_pins = self.wld_inst[0].get_pins(name)
for pin in supply_pins: