luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Correcting format of replica_pbitcell.

This commit is contained in:
Michael Timothy Grimes 2018-09-13 18:51:52 -07:00
parent 9acc8a9532
commit 43f5316eed
1 changed files with 81 additions and 81 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

162
compiler/modules/replica_pbitcell.py
View File

@ -1,82 +1,82 @@
import debug import debug
import design import design
from tech import drc, spice from tech import drc, spice
from vector import vector from vector import vector
from globals import OPTS from globals import OPTS
from pbitcell import pbitcell from pbitcell import pbitcell
class replica_pbitcell(design.design): class replica_pbitcell(design.design):
""" """
Creates a replica bitcell using pbitcell Creates a replica bitcell using pbitcell
""" """
def __init__(self): def __init__(self):
self.num_rw_ports = OPTS.num_rw_ports self.num_rw_ports = OPTS.num_rw_ports
self.num_w_ports = OPTS.num_w_ports self.num_w_ports = OPTS.num_w_ports
self.num_r_ports = OPTS.num_r_ports self.num_r_ports = OPTS.num_r_ports
self.total_ports = self.num_rw_ports + self.num_w_ports + self.num_r_ports self.total_ports = self.num_rw_ports + self.num_w_ports + self.num_r_ports
design.design.__init__(self, "replica_pbitcell") design.design.__init__(self, "replica_pbitcell")
debug.info(1, "create a replica bitcell using pbitcell with {0} rw ports, {1} w ports and {2} r ports".format(self.num_rw_ports, debug.info(1, "create a replica bitcell using pbitcell with {0} rw ports, {1} w ports and {2} r ports".format(self.num_rw_ports,
self.num_w_ports, self.num_w_ports,
self.num_r_ports)) self.num_r_ports))
self.create_netlist() self.create_netlist()
self.create_layout() self.create_layout()
def create_netlist(self): def create_netlist(self):
self.add_pins() self.add_pins()
self.add_modules() self.add_modules()
self.create_modules() self.create_modules()
def create_layout(self): def create_layout(self):
self.place_pbitcell() self.place_pbitcell()
self.route_rbc_connections() self.route_rbc_connections()
self.DRC_LVS() self.DRC_LVS()
def add_pins(self): def add_pins(self):
for port in range(self.total_ports): for port in range(self.total_ports):
self.add_pin("bl{}".format(port)) self.add_pin("bl{}".format(port))
self.add_pin("br{}".format(port)) self.add_pin("br{}".format(port))
for port in range(self.total_ports): for port in range(self.total_ports):
self.add_pin("wl{}".format(port)) self.add_pin("wl{}".format(port))
self.add_pin("vdd") self.add_pin("vdd")
self.add_pin("gnd") self.add_pin("gnd")
def add_modules(self): def add_modules(self):
self.prbc = pbitcell(replica_bitcell=True) self.prbc = pbitcell(replica_bitcell=True)
self.add_mod(self.prbc) self.add_mod(self.prbc)
self.height = self.prbc.height self.height = self.prbc.height
self.width = self.prbc.width self.width = self.prbc.width
def create_modules(self): def create_modules(self):
self.prbc_inst = self.add_inst(name="pbitcell", self.prbc_inst = self.add_inst(name="pbitcell",
mod=self.prbc) mod=self.prbc)
temp = [] temp = []
for port in range(self.total_ports): for port in range(self.total_ports):
temp.append("bl{}".format(port)) temp.append("bl{}".format(port))
temp.append("br{}".format(port)) temp.append("br{}".format(port))
for port in range(self.total_ports): for port in range(self.total_ports):
temp.append("wl{}".format(port)) temp.append("wl{}".format(port))
temp.append("vdd") temp.append("vdd")
temp.append("gnd") temp.append("gnd")
self.connect_inst(temp) self.connect_inst(temp)
def place_pbitcell(self): def place_pbitcell(self):
offset = [0,0] offset = [0,0]
self.prbc_inst.place(offset=offset) self.prbc_inst.place(offset=offset)
def route_rbc_connections(self): def route_rbc_connections(self):
for port in range(self.total_ports): for port in range(self.total_ports):
self.copy_layout_pin(self.prbc_inst, "bl{}".format(port)) self.copy_layout_pin(self.prbc_inst, "bl{}".format(port))
self.copy_layout_pin(self.prbc_inst, "br{}".format(port)) self.copy_layout_pin(self.prbc_inst, "br{}".format(port))
for port in range(self.total_ports): for port in range(self.total_ports):
self.copy_layout_pin(self.prbc_inst, "wl{}".format(port)) self.copy_layout_pin(self.prbc_inst, "wl{}".format(port))
self.copy_layout_pin(self.prbc_inst, "vdd") self.copy_layout_pin(self.prbc_inst, "vdd")
self.copy_layout_pin(self.prbc_inst, "gnd") self.copy_layout_pin(self.prbc_inst, "gnd")