From 43f5316eedc15dea4f48d32469ad1c97fecf409c Mon Sep 17 00:00:00 2001 From: Michael Timothy Grimes Date: Thu, 13 Sep 2018 18:51:52 -0700 Subject: [PATCH] Correcting format of replica_pbitcell. --- compiler/modules/replica_pbitcell.py | 162 +++++++++++++-------------- 1 file changed, 81 insertions(+), 81 deletions(-) diff --git a/compiler/modules/replica_pbitcell.py b/compiler/modules/replica_pbitcell.py index a88823f8..4b92d487 100644 --- a/compiler/modules/replica_pbitcell.py +++ b/compiler/modules/replica_pbitcell.py @@ -1,82 +1,82 @@ -import debug -import design -from tech import drc, spice -from vector import vector -from globals import OPTS -from pbitcell import pbitcell - -class replica_pbitcell(design.design): - """ - Creates a replica bitcell using pbitcell - """ - - def __init__(self): - - self.num_rw_ports = OPTS.num_rw_ports - self.num_w_ports = OPTS.num_w_ports - self.num_r_ports = OPTS.num_r_ports - self.total_ports = self.num_rw_ports + self.num_w_ports + self.num_r_ports - - design.design.__init__(self, "replica_pbitcell") - debug.info(1, "create a replica bitcell using pbitcell with {0} rw ports, {1} w ports and {2} r ports".format(self.num_rw_ports, - self.num_w_ports, - self.num_r_ports)) - - self.create_netlist() - self.create_layout() - - def create_netlist(self): - self.add_pins() - self.add_modules() - self.create_modules() - - def create_layout(self): - self.place_pbitcell() - self.route_rbc_connections() - self.DRC_LVS() - - def add_pins(self): - for port in range(self.total_ports): - self.add_pin("bl{}".format(port)) - self.add_pin("br{}".format(port)) - - for port in range(self.total_ports): - self.add_pin("wl{}".format(port)) - - self.add_pin("vdd") - self.add_pin("gnd") - - def add_modules(self): - self.prbc = pbitcell(replica_bitcell=True) - self.add_mod(self.prbc) - - self.height = self.prbc.height - self.width = self.prbc.width - - def create_modules(self): - self.prbc_inst = self.add_inst(name="pbitcell", - mod=self.prbc) - - temp = [] - for port in range(self.total_ports): - temp.append("bl{}".format(port)) - temp.append("br{}".format(port)) - for port in range(self.total_ports): - temp.append("wl{}".format(port)) - temp.append("vdd") - temp.append("gnd") - self.connect_inst(temp) - - def place_pbitcell(self): - offset = [0,0] - self.prbc_inst.place(offset=offset) - - def route_rbc_connections(self): - for port in range(self.total_ports): - self.copy_layout_pin(self.prbc_inst, "bl{}".format(port)) - self.copy_layout_pin(self.prbc_inst, "br{}".format(port)) - for port in range(self.total_ports): - self.copy_layout_pin(self.prbc_inst, "wl{}".format(port)) - self.copy_layout_pin(self.prbc_inst, "vdd") - self.copy_layout_pin(self.prbc_inst, "gnd") +import debug +import design +from tech import drc, spice +from vector import vector +from globals import OPTS +from pbitcell import pbitcell + +class replica_pbitcell(design.design): + """ + Creates a replica bitcell using pbitcell + """ + + def __init__(self): + + self.num_rw_ports = OPTS.num_rw_ports + self.num_w_ports = OPTS.num_w_ports + self.num_r_ports = OPTS.num_r_ports + self.total_ports = self.num_rw_ports + self.num_w_ports + self.num_r_ports + + design.design.__init__(self, "replica_pbitcell") + debug.info(1, "create a replica bitcell using pbitcell with {0} rw ports, {1} w ports and {2} r ports".format(self.num_rw_ports, + self.num_w_ports, + self.num_r_ports)) + + self.create_netlist() + self.create_layout() + + def create_netlist(self): + self.add_pins() + self.add_modules() + self.create_modules() + + def create_layout(self): + self.place_pbitcell() + self.route_rbc_connections() + self.DRC_LVS() + + def add_pins(self): + for port in range(self.total_ports): + self.add_pin("bl{}".format(port)) + self.add_pin("br{}".format(port)) + + for port in range(self.total_ports): + self.add_pin("wl{}".format(port)) + + self.add_pin("vdd") + self.add_pin("gnd") + + def add_modules(self): + self.prbc = pbitcell(replica_bitcell=True) + self.add_mod(self.prbc) + + self.height = self.prbc.height + self.width = self.prbc.width + + def create_modules(self): + self.prbc_inst = self.add_inst(name="pbitcell", + mod=self.prbc) + + temp = [] + for port in range(self.total_ports): + temp.append("bl{}".format(port)) + temp.append("br{}".format(port)) + for port in range(self.total_ports): + temp.append("wl{}".format(port)) + temp.append("vdd") + temp.append("gnd") + self.connect_inst(temp) + + def place_pbitcell(self): + offset = [0,0] + self.prbc_inst.place(offset=offset) + + def route_rbc_connections(self): + for port in range(self.total_ports): + self.copy_layout_pin(self.prbc_inst, "bl{}".format(port)) + self.copy_layout_pin(self.prbc_inst, "br{}".format(port)) + for port in range(self.total_ports): + self.copy_layout_pin(self.prbc_inst, "wl{}".format(port)) + self.copy_layout_pin(self.prbc_inst, "vdd") + self.copy_layout_pin(self.prbc_inst, "gnd") \ No newline at end of file