From 4377619bf6d0645950abbe92faf5a346419825b9 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Mon, 3 May 2021 14:39:51 -0700 Subject: [PATCH] fixed port_data typo --- compiler/modules/port_data.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 6f66d26f..b4320583 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -44,6 +44,8 @@ class port_data(design.design): if(cell_properties.use_strap == True and OPTS.num_ports == 1): strap = factory.create(module_type=cell_properties.strap_module, version=cell_properties.strap_version) precharge_width = bitcell.width + strap.width + else: + precharge_width = bitcell.width self.bit_offsets = [] for i in range(self.num_cols + self.num_spare_cols): self.bit_offsets.append(i * precharge_width)