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Removed dead code from delay and base module related to characterization
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@@ -366,36 +366,6 @@ class delay(simulation):
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# so it makes the search awkward
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return set(factory.get_mods(OPTS.replica_bitline))
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def get_primary_cell_mod(self, cell_mods):
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"""
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Distinguish bitcell array mod from replica bitline array.
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Assume there are no replica bitcells in the primary array.
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"""
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if len(cell_mods) == 1:
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return cell_mods[0]
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rbc_mods = factory.get_mods(OPTS.replica_bitcell)
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non_rbc_mods = []
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for bitcell in cell_mods:
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has_cell = False
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for replica_cell in rbc_mods:
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has_cell = has_cell or replica_cell.contains(bitcell, replica_cell.mods)
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if not has_cell:
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non_rbc_mods.append(bitcell)
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if len(non_rbc_mods) != 1:
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debug.error('Multiple bitcell mods found. Cannot distinguish for characterization',1)
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return non_rbc_mods[0]
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def are_mod_pins_equal(self, mods):
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"""Determines if there are pins differences in the input mods"""
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if len(mods) == 0:
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return True
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pins = mods[0].pins
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for mod in mods[1:]:
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if pins != mod.pins:
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return False
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return True
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def get_alias_in_path(self, paths, int_net, mod, exclusion_set=None):
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"""
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Finds a single alias for the int_net in given paths.
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