From 42f2ff679e6422272d18fc7f012136a82480ce03 Mon Sep 17 00:00:00 2001
From: Hunter Nichols <hznichol@ucsc.edu>
Date: Thu, 27 Aug 2020 15:40:41 -0700
Subject: [PATCH] Removed dead code from delay and base module related to
 characterization

---
 compiler/base/hierarchy_design.py | 10 ----------
 compiler/characterizer/delay.py   | 30 ------------------------------
 2 files changed, 40 deletions(-)

diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py
index 79b5a53a..ea6a3f44 100644
--- a/compiler/base/hierarchy_design.py
+++ b/compiler/base/hierarchy_design.py
@@ -222,16 +222,6 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
         return self == mod and \
                child_net.lower() == alias_net.lower() and \
                parent_net.lower() == alias_net.lower()
-           
-    def get_mod_net(self, parent_net, child_inst, child_conns):
-        """
-        Given an instance and net, returns the internal net in the mod
-        corresponding to input net.
-        """
-        for conn, pin in zip(child_conns, child_inst.mod.pins):
-            if parent_net.lower() == conn.lower():
-                return pin
-        return None
       
     def translate_nets(self, subinst_ports, port_dict, inst_name):
         """Converts connection names to their spice hierarchy equivalent"""
diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py
index da1b8147..556e02bb 100644
--- a/compiler/characterizer/delay.py
+++ b/compiler/characterizer/delay.py
@@ -366,36 +366,6 @@ class delay(simulation):
         # so it makes the search awkward
         return set(factory.get_mods(OPTS.replica_bitline))
         
-    def get_primary_cell_mod(self, cell_mods):
-        """
-        Distinguish bitcell array mod from replica bitline array.
-        Assume there are no replica bitcells in the primary array.
-        """
-        if len(cell_mods) == 1:
-            return cell_mods[0]
-        rbc_mods = factory.get_mods(OPTS.replica_bitcell)
-        non_rbc_mods = []
-        for bitcell in cell_mods:
-            has_cell = False
-            for replica_cell in rbc_mods:
-                has_cell = has_cell or replica_cell.contains(bitcell, replica_cell.mods)
-            if not has_cell:
-                non_rbc_mods.append(bitcell)
-        if len(non_rbc_mods) != 1:
-            debug.error('Multiple bitcell mods found. Cannot distinguish for characterization',1)
-        return non_rbc_mods[0]
-        
-    def are_mod_pins_equal(self, mods):
-        """Determines if there are pins differences in the input mods"""
-        
-        if len(mods) == 0:
-            return True
-        pins = mods[0].pins
-        for mod in mods[1:]:
-            if pins != mod.pins:
-                return False
-        return True
-        
     def get_alias_in_path(self, paths, int_net, mod, exclusion_set=None): 
         """
         Finds a single alias for the int_net in given paths.