Fixing netlist_only errors. Removing netlist_only option from ptx because it must always generate layout for pbitcell. gds_write, drc check, and lvs check in local_check() are now in a 'if not OPTS.netlist_only' conditional. These functions will generate errors in netlist_only mode since there is no gds layout to write or check.

compiler/pgates/pbitcell.py

@@ -70,6 +70,9 @@ class pbitcell(design.design):
             self.route_read_access()
         self.extend_well()
         
+        # in netlist_only mode, calling offset_all_coordinates will not be possible
+        # this function is not needed to calculate the dimensions of pbitcell in netlist_only mode though
+        if not OPTS.netlist_only:
             self.offset_all_coordinates()
         self.DRC_LVS()
     

compiler/pgates/ptx.py

@@ -41,7 +41,8 @@ class ptx(design.design):
         self.num_contacts = num_contacts
 
         self.create_netlist()
-        if not OPTS.netlist_only:
+        # We must always create ptx layout for pbitcell
+        # some transistor sizes in other netlist depend on pbitcell
         self.create_layout()
 
 

compiler/tests/testutils.py

@@ -29,6 +29,8 @@ class openram_test(unittest.TestCase):
         tempgds = OPTS.openram_temp + "temp.gds"
 
         a.sp_write(tempspice)
+        # cannot write gds in netlist_only mode
+        if not OPTS.netlist_only:
             a.gds_write(tempgds)
 
             import verify