diff --git a/compiler/pgates/pbitcell.py b/compiler/pgates/pbitcell.py
index 24fdfb60..1eac5d3c 100644
--- a/compiler/pgates/pbitcell.py
+++ b/compiler/pgates/pbitcell.py
@@ -70,7 +70,10 @@ class pbitcell(design.design):
             self.route_read_access()
         self.extend_well()
         
-        self.offset_all_coordinates()
+        # in netlist_only mode, calling offset_all_coordinates will not be possible
+        # this function is not needed to calculate the dimensions of pbitcell in netlist_only mode though
+        if not OPTS.netlist_only:
+            self.offset_all_coordinates()
         self.DRC_LVS()
     
     def add_pins(self):
diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py
index e7fcd5f4..e5a1a51b 100644
--- a/compiler/pgates/ptx.py
+++ b/compiler/pgates/ptx.py
@@ -41,8 +41,9 @@ class ptx(design.design):
         self.num_contacts = num_contacts
 
         self.create_netlist()
-        if not OPTS.netlist_only:
-            self.create_layout()
+        # We must always create ptx layout for pbitcell
+        # some transistor sizes in other netlist depend on pbitcell
+        self.create_layout()
 
 
     
diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py
index e1c02f45..19d1fe3d 100644
--- a/compiler/tests/testutils.py
+++ b/compiler/tests/testutils.py
@@ -29,17 +29,19 @@ class openram_test(unittest.TestCase):
         tempgds = OPTS.openram_temp + "temp.gds"
 
         a.sp_write(tempspice)
-        a.gds_write(tempgds)
+        # cannot write gds in netlist_only mode
+        if not OPTS.netlist_only:
+            a.gds_write(tempgds)
 
-        import verify
-        result=verify.run_drc(a.name, tempgds)
-        if result != 0:
-            self.fail("DRC failed: {}".format(a.name))
+            import verify
+            result=verify.run_drc(a.name, tempgds)
+            if result != 0:
+                self.fail("DRC failed: {}".format(a.name))
 
             
-        result=verify.run_lvs(a.name, tempgds, tempspice, final_verification)
-        if result != 0:
-            self.fail("LVS mismatch: {}".format(a.name))
+            result=verify.run_lvs(a.name, tempgds, tempspice, final_verification)
+            if result != 0:
+                self.fail("LVS mismatch: {}".format(a.name))
 
         if OPTS.purge_temp:
             self.cleanup()