rom compiler top level

compiler/modules/rom_base_array.py

@@ -10,7 +10,7 @@
 import math
 from .bitcell_base_array import bitcell_base_array
 from openram.base import vector
-from openram import OPTS
+from openram import OPTS, debug
 from openram.sram_factory import factory
 from openram.tech import drc, layer
 
@@ -35,6 +35,7 @@ class rom_base_array(bitcell_base_array):
             self.array_col_size = self.column_size
         self.create_all_bitline_names()
         self.create_all_wordline_names()
+        # debug.info(1, "ROM array with rows: {0}, cols: {1}".format(self.row_size, self.column_size))
         self.create_netlist()
         self.create_layout()
 
@@ -148,6 +149,7 @@ class rom_base_array(bitcell_base_array):
 
         # when col = 0, bl_h is connected to precharge, otherwise connect to previous bl connection
         # when col = col_size - 1 connected column_sizeto gnd otherwise create new bl connection
+        # debug.info(1, "Create cell: r{0}, c{1}".format(row, col))
         if row == self.row_size:
 
             bl_l = self.int_bl_list[col]