mirror of https://github.com/VLSIDA/OpenRAM.git
340 lines
13 KiB
Python
340 lines
13 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import math
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from .bitcell_base_array import bitcell_base_array
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from openram.base import vector
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from openram import OPTS, debug
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from openram.sram_factory import factory
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from openram.tech import drc, layer
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class rom_base_array(bitcell_base_array):
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def __init__(self, rows, cols, strap_spacing, bitmap, tap_spacing = 4, name="", bitline_layer="m1", wordline_layer="m2", tap_direction="row", pitch_match=False):
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super().__init__(name=name, rows=rows, cols=cols, column_offset=0)
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self.data = bitmap
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self.tap_direction = tap_direction
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self.pitch_match = pitch_match
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self.bitline_layer = bitline_layer
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self.strap_spacing = strap_spacing
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self.wordline_layer = wordline_layer
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self.data_col_size = self.column_size
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self.tap_spacing = tap_spacing
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if strap_spacing != 0:
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self.array_col_size = self.column_size + math.ceil(self.column_size / strap_spacing)
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else:
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self.array_col_size = self.column_size
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self.create_all_bitline_names()
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self.create_all_wordline_names()
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# debug.info(1, "ROM array with rows: {0}, cols: {1}".format(self.row_size, self.column_size))
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self.create_netlist()
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_cell_instances()
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self.create_precharge_inst()
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def create_layout(self):
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self.create_layout_constants()
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self.place_array()
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if self.tap_direction == "row":
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self.route_pitch_offsets()
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self.place_precharge()
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self.place_wordline_contacts()
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self.place_bitline_contacts()
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self.route_precharge()
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self.add_boundary()
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self.place_rails()
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self.connect_taps()
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def add_boundary(self):
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ll = self.find_lowest_coords()
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m1_offset = self.m1_width
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self.translate_all(vector(0, ll.y + 0.5 * m1_offset))
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ur = self.find_highest_coords()
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ur = vector(ur.x, ur.y - self.m1_width)
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super().add_boundary(vector(0, 0), ur)
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self.width = ur.x
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self.height = ur.y
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def add_modules(self):
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self.zero_cell = factory.create(module_name="rom_base_zero_cell",
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module_type="rom_base_cell",
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bitline_layer=self.bitline_layer,
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bit_value=0)
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self.one_cell = factory.create(module_name="rom_base_one_cell",
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module_type="rom_base_cell",
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bitline_layer=self.bitline_layer,
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bit_value=1)
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if self.tap_direction == "row":
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self.poly_tap = factory.create(module_type="rom_poly_tap")
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else:
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self.poly_tap = factory.create(module_type="rom_poly_tap", add_tap=True)
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self.precharge_array = factory.create(module_type="rom_precharge_array",
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cols=self.column_size,
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strap_spacing=self.strap_spacing,
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bitline_layer=self.bitline_layer,
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strap_layer=self.wordline_layer,
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tap_direction=self.tap_direction)
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def create_layout_constants(self):
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self.route_width = drc("minwidth_" + self.bitline_layer)
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self.route_pitch = drc("{0}_to_{0}".format(self.bitline_layer))
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def add_pins(self):
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for bl_name in self.get_bitline_names():
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self.add_pin(bl_name, "OUTPUT")
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for wl_name in self.get_wordline_names():
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self.add_pin(wl_name, "INPUT")
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self.add_pin("precharge", "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def create_cell_instances(self):
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self.tap_inst = {}
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self.tap_list = []
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self.cell_inst = {}
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self.cell_list = []
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self.current_row = 0
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# list of current bitline interconnect nets,
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# starts as the same as the bitline list and is updated when new insts of cells are added
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self.int_bl_list = self.bitline_names[0].copy()
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for row in range(self.row_size + 1):
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row_list = []
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for col in range(self.column_size):
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if col % self.strap_spacing == 0:
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self.create_poly_tap(row, col)
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new_inst = self.create_cell(row, col)
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self.cell_inst[row, col] = new_inst
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row_list.append(new_inst)
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name = "tap_r{0}_c{1}".format(row, self.array_col_size)
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new_tap = self.add_inst(name=name, mod=self.poly_tap)
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self.tap_inst[row, self.column_size] = new_tap
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self.tap_list.append(new_tap)
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self.connect_inst([])
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self.cell_list.append(row_list)
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def create_poly_tap(self, row, col):
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name = "tap_r{0}_c{1}".format(row, col)
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new_tap = self.add_inst(name=name, mod=self.poly_tap)
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self.tap_inst[row, col]=new_tap
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self.tap_list.append(new_tap)
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self.connect_inst([])
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def create_cell(self, row, col):
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name = "bit_r{0}_c{1}".format(row, col)
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# when col = 0, bl_h is connected to precharge, otherwise connect to previous bl connection
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# when col = col_size - 1 connected column_sizeto gnd otherwise create new bl connection
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# debug.info(1, "Create cell: r{0}, c{1}".format(row, col))
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if row == self.row_size:
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bl_l = self.int_bl_list[col]
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bl_h = "gnd"
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else:
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bl_l = self.int_bl_list[col]
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if self.data[row][col] == 1:
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self.int_bl_list[col] = "bl_int_{0}_{1}".format(row, col)
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bl_h = self.int_bl_list[col]
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# Final row of dummy nmos that contains only 1s, acts to prevent shorting bl to ground when precharging
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if row == self.row_size:
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new_inst = self.add_inst(name=name, mod=self.one_cell)
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self.connect_inst([bl_h, bl_l, "precharge", "gnd"])
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elif self.data[row][col] == 1:
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new_inst = self.add_inst(name=name, mod=self.one_cell)
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self.connect_inst([bl_h, bl_l, self.wordline_names[0][row], "gnd"])
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else:
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new_inst = self.add_inst(name=name, mod=self.zero_cell)
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self.connect_inst([bl_h, self.wordline_names[0][row], "gnd"])
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return new_inst
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def create_precharge_inst(self):
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prechrg_pins = self.bitline_names[0].copy()
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prechrg_pins.append("precharge")
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prechrg_pins.append("vdd")
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self.precharge_inst = self.add_inst(name="bitcell_array_precharge", mod=self.precharge_array)
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self.connect_inst(prechrg_pins)
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def create_all_bitline_names(self):
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for col in range(self.column_size):
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for port in self.all_ports:
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self.bitline_names[port].extend(["bl_{0}_{1}".format(port, col)])
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# Make a flat list too
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self.all_bitline_names = [x for sl in zip(*self.bitline_names) for x in sl]
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def place_rails(self):
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via_width = drc("m2_enclose_via1") * 0.5 + drc("minwidth_via1")
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pitch = drc["{0}_to_{0}".format(self.wordline_layer)]
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for i in range(self.column_size):
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drain = self.cell_list[self.row_size][i].get_pin("D")
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gnd_pos = drain.center() + vector(0, pitch + via_width + self.route_pitch)
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self.add_layout_pin_rect_center(text="gnd", layer=self.bitline_layer, offset=gnd_pos)
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self.route_horizontal_pins("gnd", insts=[self], yside="cy")
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self.copy_layout_pin(self.precharge_inst, "vdd")
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def place_array(self):
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self.cell_pos = {}
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self.strap_pos = {}
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pitch_offset = 0
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for row in range(self.row_size + 1):
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if row % self.tap_spacing == 0 and self.pitch_match and row != self.row_size:
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pitch_offset += self.active_contact.width + self.active_space
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cell_y = row * (self.zero_cell.height) + pitch_offset
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cell_x = 0
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for col in range(self.column_size):
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if col % self.strap_spacing == 0:
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self.strap_pos[row, col] = vector(cell_x, cell_y)
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self.tap_inst[row, col].place(self.strap_pos[row, col])
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if self.tap_direction == "col":
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cell_x += self.poly_tap.pitch_offset
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self.cell_pos[row, col] = vector(cell_x, cell_y)
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self.cell_inst[row, col].place(self.cell_pos[row, col])
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cell_x += self.zero_cell.width
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self.strap_pos[row, self.column_size] = vector(cell_x, cell_y)
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self.tap_inst[row, self.column_size].place(self.strap_pos[row, self.column_size])
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def route_pitch_offsets(self):
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for row in range(0 , self.row_size, self.tap_spacing):
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for col in range(self.column_size):
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cell = self.cell_inst[row, col]
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source = cell.get_pin("S")
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if row != 0:
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drain = self.cell_inst[row - 1, col].get_pin("D")
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start = vector(drain.cx(), source.cy())
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end = drain.center()
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self.add_segment_center(self.bitline_layer, start, end)
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self.place_well_tap(row, col)
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def place_well_tap(self, row, col):
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cell = self.cell_inst[row, col]
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source = cell.get_pin("S")
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if col != self.column_size - 1:
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tap_x = (self.cell_inst[row , col + 1].get_pin("S").cx() + source.cx()) * 0.5
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else:
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tap_x = cell.rx() + self.active_space
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if row != 0:
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drain = self.cell_inst[row - 1, col].get_pin("D")
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tap_y = (source.cy() + drain.cy()) * 0.5
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else:
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tap_y = source.cy() - self.contact_width - 2 * self.active_enclose_contact - self.active_space
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tap_pos = vector(tap_x, tap_y)
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self.add_via_center(layers=self.active_stack,
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offset=tap_pos,
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implant_type="p",
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well_type="p",
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directions="nonpref")
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self.add_via_stack_center(offset=tap_pos,
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from_layer=self.active_stack[2],
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to_layer=self.wordline_layer)
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self.add_layout_pin_rect_center("gnd", self.wordline_layer, tap_pos)
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def place_precharge(self):
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self.precharge_offset = vector(0, - self.precharge_inst.height - self.zero_cell.nmos.end_to_contact - 2 * drc["nwell_enclose_active"] - 3 * self.m1_pitch)
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self.precharge_inst.place(offset=self.precharge_offset)
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self.copy_layout_pin(self.precharge_inst, "vdd")
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self.copy_layout_pin(self.precharge_inst, "gate", "precharge")
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def place_wordline_contacts(self):
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for wl in range(self.row_size):
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self.copy_layout_pin(self.tap_inst[wl, 0], "poly_tap", self.wordline_names[0][wl])
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def place_bitline_contacts(self):
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rail_y = self.precharge_inst.get_pins("vdd")[0].cy()
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for bl in range(self.column_size):
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src_pin = self.cell_list[0][bl].get_pin("S")
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prechg_pin_name = "pre_bl{0}_out".format(bl)
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pre_pin = self.precharge_inst.get_pin(prechg_pin_name)
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middle_offset = (src_pin.cy() - pre_pin.cy() ) * 0.5
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corrected = vector(src_pin.cx(), src_pin.cy() - middle_offset)
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output_pos = vector(corrected.x, rail_y)
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self.add_segment_center(self.bitline_layer, corrected, output_pos)
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self.add_layout_pin_rect_center(self.bitline_names[0][bl], self.bitline_layer, output_pos )
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def route_precharge(self):
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for bl in range(self.column_size):
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bl_pin = self.cell_list[0][bl].get_pin("S")
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prechg_pin = "pre_bl{0}_out".format(bl)
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pre_out_pin = self.precharge_inst.get_pin(prechg_pin)
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bl_start = bl_pin.center()
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bl_end = vector(bl_start.x, pre_out_pin.cy())
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self.add_segment_center(self.bitline_layer, bl_start, bl_end)
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upper_precharge = self.precharge_inst.get_pin("precharge_r")
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lower_precharge = self.tap_inst[self.row_size, self.column_size ].get_pin("poly_tap")
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if self.pitch_match:
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wire_offset = 2 * self.m1_pitch
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else:
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wire_offset = 3 * self.m1_pitch
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start = upper_precharge.center()
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end = lower_precharge.center()
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mid1 = start + vector(wire_offset, 0)
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mid2 = end + vector(wire_offset, 0)
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self.add_path(layer="m1", coordinates=[start, mid1, mid2, end])
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self.add_layout_pin_rect_center(text="precharge_r", layer="m1", offset=mid1)
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def connect_taps(self):
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array_pins = [self.tap_list[i].get_pin("poly_tap") for i in range(len(self.tap_list))]
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self.connect_row_pins(layer=self.wordline_layer, pins=array_pins, name=None, round=False)
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if self.tap_direction == "col":
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self.route_vertical_pins("active_tap", insts=self.tap_list, layer=self.supply_stack[0], full_width=False) |