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https://github.com/VLSIDA/OpenRAM.git
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rom compiler top level
This commit is contained in:
Jacob Walker
@@ -72,6 +72,7 @@ from .replica_pbitcell import *
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from .row_cap_array import *
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from .row_cap_bitcell_1port import *
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from .row_cap_bitcell_2port import *
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from .rom_base_bank import *
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from .sense_amp_array import *
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from .sense_amp import *
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from .tri_gate_array import *
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@@ -10,7 +10,7 @@
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import math
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from .bitcell_base_array import bitcell_base_array
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from openram.base import vector
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from openram import OPTS
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from openram import OPTS, debug
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from openram.sram_factory import factory
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from openram.tech import drc, layer
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@@ -35,6 +35,7 @@ class rom_base_array(bitcell_base_array):
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self.array_col_size = self.column_size
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self.create_all_bitline_names()
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self.create_all_wordline_names()
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# debug.info(1, "ROM array with rows: {0}, cols: {1}".format(self.row_size, self.column_size))
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self.create_netlist()
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self.create_layout()
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@@ -148,6 +149,7 @@ class rom_base_array(bitcell_base_array):
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# when col = 0, bl_h is connected to precharge, otherwise connect to previous bl connection
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# when col = col_size - 1 connected column_sizeto gnd otherwise create new bl connection
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# debug.info(1, "Create cell: r{0}, c{1}".format(row, col))
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if row == self.row_size:
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bl_l = self.int_bl_list[col]
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@@ -6,10 +6,11 @@
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# All rights reserved.
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#
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import datetime
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from math import ceil, log, sqrt
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from openram.base import vector
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from openram.base import design
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from openram import OPTS, debug
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from openram import OPTS, debug, print_time
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from openram.sram_factory import factory
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from openram.tech import drc, layer, parameter
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@@ -21,120 +22,82 @@ class rom_base_bank(design):
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word size is in bytes
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"""
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def __init__(self, strap_spacing=0, data_file=None, name="", word_size=2):
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def __init__(self, name, rom_config):
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super().__init__(name=name)
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self.word_size = word_size * 8
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self.read_binary(word_size=word_size, data_file=data_file, scramble_bits=True, endian="little")
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self.rom_config = rom_config
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rom_config.set_local_config(self)
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self.word_size = self.word_bits
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# self.read_binary(word_size=word_size, data_file=data_file, scramble_bits=True, endian="little")
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# debug.info(1, "Rom data: {}".format(self.data))
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self.num_outputs = self.rows
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self.num_inputs = ceil(log(self.rows, 2))
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self.col_bits = ceil(log(self.words_per_row, 2))
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self.row_bits = self.num_inputs
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# self.data = [[0, 1, 0, 1], [1, 1, 1, 1], [1, 1, 0, 0], [0, 0, 1, 0]]
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self.strap_spacing = strap_spacing
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self.tap_spacing = 8
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self.tap_spacing = self.strap_spacing
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try:
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from openram.tech import power_grid
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self.supply_stack = power_grid
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except ImportError:
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# if no power_grid is specified by tech we use sensible defaults
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# Route a M3/M4 grid
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self.supply_stack = self.m3_stack
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self.interconnect_layer = "m1"
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self.bitline_layer = "m1"
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self.wordline_layer = "m2"
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if "li" in layer:
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self.route_stack = self.m1_stack
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else:
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self.route_stack = self.m2_stack
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self.route_layer = self.route_stack[0]
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self.setup_layout_constants()
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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"""
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Reads a hexadecimal file from a given directory to be used as the data written to the ROM
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endian is either "big" or "little"
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word_size is the number of bytes per word
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sets the row and column size based on the size of binary input, tries to keep array as square as possible,
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"""
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def read_binary(self, data_file, word_size=2, endian="big", scramble_bits=False):
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# Read data as hexidecimal text file
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hex_file = open(data_file, 'r')
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hex_data = hex_file.read()
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# Convert from hex into an int
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data_int = int(hex_data, 16)
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# Then from int into a right aligned, zero padded string
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bin_string = bin(data_int)[2:].zfill(len(hex_data) * 4)
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# Then turn the string into a list of ints
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bin_data = list(bin_string)
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bin_data = [int(x) for x in bin_data]
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# data size in bytes
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data_size = len(bin_data) / 8
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num_words = int(data_size / word_size)
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bytes_per_col = sqrt(num_words)
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self.words_per_row = int(ceil(bytes_per_col /(2*word_size)))
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bits_per_row = self.words_per_row * word_size * 8
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self.cols = bits_per_row
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self.rows = int(num_words / (self.words_per_row))
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chunked_data = []
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for i in range(0, len(bin_data), bits_per_row):
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row_data = bin_data[i:i + bits_per_row]
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if len(row_data) < bits_per_row:
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row_data = [0] * (bits_per_row - len(row_data)) + row_data
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chunked_data.append(row_data)
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# if endian == "big":
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self.data = chunked_data
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if scramble_bits:
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scrambled_chunked = []
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for row_data in chunked_data:
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scambled_data = []
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for bit in range(self.word_size):
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for word in range(self.words_per_row):
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scambled_data.append(row_data[bit + word * self.word_size])
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scrambled_chunked.append(scambled_data)
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self.data = scrambled_chunked
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# self.data.reverse()
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debug.info(1, "Read rom binary: length {0} bytes, {1} words, set number of cols to {2}, rows to {3}, with {4} words per row".format(data_size, num_words, self.cols, self.rows, self.words_per_row))
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def create_netlist(self):
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start_time = datetime.datetime.now()
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self.add_modules()
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self.add_pins()
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self.create_instances()
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if not OPTS.is_unit_test:
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print_time("Submodules", datetime.datetime.now(), start_time)
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def create_layout(self):
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self.create_instances()
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start_time = datetime.datetime.now()
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self.setup_layout_constants()
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self.place_instances()
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if not OPTS.is_unit_test:
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print_time("Placement", datetime.datetime.now(), start_time)
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start_time = datetime.datetime.now()
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self.route_layout()
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if not OPTS.is_unit_test:
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print_time("Routing", datetime.datetime.now(), start_time)
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self.height = self.array_inst.height
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self.width = self.array_inst.width
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self.add_boundary()
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start_time = datetime.datetime.now()
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if not OPTS.is_unit_test:
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# We only enable final verification if we have routed the design
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# Only run this if not a unit test, because unit test will also verify it.
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self.DRC_LVS(final_verification=OPTS.route_supplies, force_check=OPTS.check_lvsdrc)
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print_time("Verification", datetime.datetime.now(), start_time)
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def route_layout(self):
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self.route_decode_outputs()
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self.route_precharge()
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self.route_clock()
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self.route_array_outputs()
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self.place_top_level_pins()
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self.route_supplies()
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self.route_output_buffers()
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self.height = self.array_inst.height
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self.width = self.array_inst.width
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self.add_boundary()
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def setup_layout_constants(self):
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self.route_layer_width = drc["minwidth_{}".format(self.route_stack[0])]
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@@ -166,7 +129,7 @@ class rom_base_bank(design):
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# in sky130 the address control buffer is composed of 2 size 2 NAND gates,
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# with a beta of 3, each of these gates has gate capacitance of 2 min sized inverters, therefor a load of 4
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addr_control_buffer_effort = parameter['beta'] + 1
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# a single min sized nmos makes up 1/4 of the input capacitance of a min sized inverter
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bitcell_effort = 0.25
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@@ -492,12 +455,72 @@ class rom_base_bank(design):
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pin_num = msb - self.col_bits
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self.copy_layout_pin(self.decode_inst, "A{}".format(pin_num), name)
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def route_supplies(self):
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for inst in self.insts:
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if not inst.mod.name.__contains__("contact"):
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self.copy_layout_pin(inst, "vdd")
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self.copy_layout_pin(inst, "gnd")
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self.copy_layout_pin(inst, "gnd")
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# """
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# Reads a hexadecimal file from a given directory to be used as the data written to the ROM
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# endian is either "big" or "little"
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# word_size is the number of bytes per word
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# sets the row and column size based on the size of binary input, tries to keep array as square as possible,
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# """
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# def read_binary(self, data_file, word_size=2, endian="big", scramble_bits=False):
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# # Read data as hexidecimal text file
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# hex_file = open(data_file, 'r')
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# hex_data = hex_file.read()
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# # Convert from hex into an int
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# data_int = int(hex_data, 16)
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# # Then from int into a right aligned, zero padded string
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# bin_string = bin(data_int)[2:].zfill(len(hex_data) * 4)
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# # Then turn the string into a list of ints
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# bin_data = list(bin_string)
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# bin_data = [int(x) for x in bin_data]
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# # data size in bytes
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# data_size = len(bin_data) / 8
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# num_words = int(data_size / word_size)
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# bytes_per_col = sqrt(num_words)
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# self.words_per_row = int(ceil(bytes_per_col /(2*word_size)))
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# bits_per_row = self.words_per_row * word_size * 8
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# self.cols = bits_per_row
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# self.rows = int(num_words / (self.words_per_row))
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# chunked_data = []
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# for i in range(0, len(bin_data), bits_per_row):
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# row_data = bin_data[i:i + bits_per_row]
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# if len(row_data) < bits_per_row:
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# row_data = [0] * (bits_per_row - len(row_data)) + row_data
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# chunked_data.append(row_data)
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# # if endian == "big":
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# self.data = chunked_data
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# if scramble_bits:
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# scrambled_chunked = []
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# for row_data in chunked_data:
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# scambled_data = []
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# for bit in range(self.word_size):
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# for word in range(self.words_per_row):
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# scambled_data.append(row_data[bit + word * self.word_size])
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# scrambled_chunked.append(scambled_data)
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# self.data = scrambled_chunked
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# # self.data.reverse()
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# debug.info(1, "Read rom binary: length {0} bytes, {1} words, set number of cols to {2}, rows to {3}, with {4} words per row".format(data_size, num_words, self.cols, self.rows, self.words_per_row))
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