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Shrunk address register in multibank verilog

This commit is contained in:
Bugra Onal 2022-07-21 15:18:04 -07:00
parent 6b5fe8a096
commit 3f1a5a2051
2 changed files with 6 additions and 6 deletions
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6
compiler/modules/sram_multibank_template.v
View File

@ -72,7 +72,7 @@ module {{ module_name }} (
{% endfor %} {% endfor %}
{% for port in ports %} {% for port in ports %}
reg [ADDR_WIDTH - 1 : 0] addr{{ port }}_reg; reg [BANK_SEL - 1 : 0] addr{{ port }}_reg;
{% for bank in banks %} {% for bank in banks %}
wire [DATA_WIDTH - 1 : 0] dout{{ port }}_bank{{ bank }}; wire [DATA_WIDTH - 1 : 0] dout{{ port }}_bank{{ bank }};
@ -122,13 +122,13 @@ module {{ module_name }} (
{% for port in ports %} {% for port in ports %}
always @(posedge clk{{ port }}) begin always @(posedge clk{{ port }}) begin
addr{{ port }}_reg <= addr{{ port }}; addr{{ port }}_reg <= addr{{ port }}[ADDR_WIDTH - 1 : ADDR_WIDTH - BANK_SEL];
end end
{% endfor %} {% endfor %}
{% for port in ports %} {% for port in ports %}
always @(*) begin always @(*) begin
case (addr{{ port }}_reg[ADDR_WIDTH - 1 : ADDR_WIDTH - BANK_SEL]) case (addr{{ port }}_reg)
{% for bank in banks %} {% for bank in banks %}
{{ bank }}: begin {{ bank }}: begin
dout{{ port }} = dout{{ port }}_bank{{ bank }}; dout{{ port }} = dout{{ port }}_bank{{ bank }};

6
compiler/tests/golden/sram_2_16_2_scn4m_subm.v
View File

@ -29,7 +29,7 @@ module sram (
input web0; input web0;
output reg [DATA_WIDTH - 1 : 0] dout0; output reg [DATA_WIDTH - 1 : 0] dout0;
reg [ADDR_WIDTH - 1 : 0] addr0_reg; reg [BANK_SEL - 1 : 0] addr0_reg;
wire [DATA_WIDTH - 1 : 0] dout0_bank0; wire [DATA_WIDTH - 1 : 0] dout0_bank0;
@ -70,11 +70,11 @@ module sram (
); );
always @(posedge clk0) begin always @(posedge clk0) begin
addr0_reg <= addr0; addr0_reg <= addr0[ADDR_WIDTH - 1 : ADDR_WIDTH - BANK_SEL];
end end
always @(*) begin always @(*) begin
case (addr0_reg[ADDR_WIDTH - 1 : ADDR_WIDTH - BANK_SEL]) case (addr0_reg)
0: begin 0: begin
dout0 = dout0_bank0; dout0 = dout0_bank0;
end end