From 3f1a5a20515c43f18af697ea906f3725368c260f Mon Sep 17 00:00:00 2001
From: Bugra Onal <onalbugra@gmail.com>
Date: Thu, 21 Jul 2022 15:18:04 -0700
Subject: [PATCH] Shrunk address register in multibank verilog

---
 compiler/modules/sram_multibank_template.v     | 6 +++---
 compiler/tests/golden/sram_2_16_2_scn4m_subm.v | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/compiler/modules/sram_multibank_template.v b/compiler/modules/sram_multibank_template.v
index d146cba4..85881a43 100644
--- a/compiler/modules/sram_multibank_template.v
+++ b/compiler/modules/sram_multibank_template.v
@@ -72,7 +72,7 @@ module {{ module_name }}  (
 {% endfor %}
 
 {% for port in ports %}
-  reg [ADDR_WIDTH - 1 : 0] addr{{ port }}_reg;
+  reg [BANK_SEL - 1 : 0] addr{{ port }}_reg;
 
 {% for bank in banks %}
   wire [DATA_WIDTH - 1 : 0] dout{{ port }}_bank{{ bank }};
@@ -122,13 +122,13 @@ module {{ module_name }}  (
 
 {% for port in ports %}
   always @(posedge clk{{ port }}) begin
-    addr{{ port }}_reg <= addr{{ port }};
+    addr{{ port }}_reg <= addr{{ port }}[ADDR_WIDTH - 1 : ADDR_WIDTH - BANK_SEL];
   end
 {% endfor %}
 
 {% for port in ports %}
   always @(*) begin
-    case (addr{{ port }}_reg[ADDR_WIDTH - 1 : ADDR_WIDTH - BANK_SEL])
+    case (addr{{ port }}_reg)
 {% for bank in banks %}
       {{ bank }}: begin
         dout{{ port }} = dout{{ port }}_bank{{ bank }};
diff --git a/compiler/tests/golden/sram_2_16_2_scn4m_subm.v b/compiler/tests/golden/sram_2_16_2_scn4m_subm.v
index 1cfc4a58..92c18777 100644
--- a/compiler/tests/golden/sram_2_16_2_scn4m_subm.v
+++ b/compiler/tests/golden/sram_2_16_2_scn4m_subm.v
@@ -29,7 +29,7 @@ module sram  (
   input web0;
   output reg [DATA_WIDTH - 1 : 0] dout0;
 
-  reg [ADDR_WIDTH - 1 : 0] addr0_reg;
+  reg [BANK_SEL - 1 : 0] addr0_reg;
 
   wire [DATA_WIDTH - 1 : 0] dout0_bank0;
 
@@ -70,11 +70,11 @@ module sram  (
   );
 
   always @(posedge clk0) begin
-    addr0_reg <= addr0;
+    addr0_reg <= addr0[ADDR_WIDTH - 1 : ADDR_WIDTH - BANK_SEL];
   end
 
   always @(*) begin
-    case (addr0_reg[ADDR_WIDTH - 1 : ADDR_WIDTH - BANK_SEL])
+    case (addr0_reg)
       0: begin
         dout0 = dout0_bank0;
       end