luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-02 11:08:01 +02:00
Code Issues Packages Projects Releases Wiki Activity

Add conditional spare row/col to a couple unit tests

Browse Source
This commit is contained in:
mrg
2021-07-01 12:49:30 -07:00
parent 2711093442
commit 3d2b192682
2 changed files with 22 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/tests/05_bitcell_array_test.py
+9 -1
View File
@@ -23,7 +23,15 @@ class array_test(openram_test):
globals.init_openram(config_file)
debug.info(2, "Testing 8x8 array for 6t_cell")
a = factory.create(module_type="bitcell_array", cols=8, rows=8)
if OPTS.tech_name == "sky130":
num_spare_rows = 1
num_spare_cols = 1
else:
num_spare_rows = 0
num_spare_cols = 0
a = factory.create(module_type="bitcell_array", cols=8 + num_spare_cols, rows=8 + num_spare_rows)
self.local_check(a)
globals.end_openram()