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Change default col mux size to 2. Add some comments.
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@@ -61,8 +61,7 @@ class single_level_column_mux_array(design.design):
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def add_modules(self):
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# FIXME: Why is this 8x?
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self.mux = single_level_column_mux(tx_size=8, bitcell_bl=self.bitcell_bl, bitcell_br=self.bitcell_br)
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self.mux = single_level_column_mux(bitcell_bl=self.bitcell_bl, bitcell_br=self.bitcell_br)
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self.add_mod(self.mux)
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