add simple sram sizing for netlist only

2026-09-03 08:27:11 +02:00 · 2020-02-06 12:10:49 +00:00
parent 18573c0e42
commit 3a06141030
3 changed files with 23 additions and 6 deletions
@@ -57,6 +57,7 @@ class bank(design.design):


    def create_netlist(self):
+
        self.compute_sizes()
        self.add_modules()
        self.add_pins() # Must create the replica bitcell array first