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precharge array test passing sky130

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This commit is contained in:
Jacob Walker
2023-03-30 11:30:50 -07:00
parent 92251fe61e
commit 382c91f342
8 changed files with 19 additions and 17 deletions
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compiler/modules/rom_base_array.py
+1 -1
View File
@@ -89,7 +89,7 @@ class rom_base_array(bitcell_base_array):
self.precharge_array = factory.create(module_type="rom_precharge_array",
cols=self.column_size,
strap_spacing=self.strap_spacing,
route_layer=self.bitline_layer,
bitline_layer=self.bitline_layer,
strap_layer=self.wordline_layer,
tap_direction=self.tap_direction)
compiler/modules/rom_base_cell.py
+1 -1
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@@ -101,7 +101,7 @@ class rom_base_cell(design):
# self.add_rect_center("poly", poly_offset, self.poly_extend_active_spacing, self.poly_width)
self.cell_inst.place(tx_offset, rotate=90)
# self.add_label("CELL ZERO", self.route_layer)
self.copy_layout_pin(self.cell_inst, "S", "S")
self.copy_layout_pin(self.cell_inst, "D", "D")
self.source_pos = self.cell_inst.get_pin("S").center()
compiler/modules/rom_precharge_array.py
+10 -8
View File
@@ -17,17 +17,22 @@ class rom_precharge_array(design):
"""
An array of inverters to create the inverted address lines for the rom decoder
"""
def __init__(self, cols, name="", route_layer="li", strap_spacing=None, strap_layer="m2", tap_direction="row"):
def __init__(self, cols, name="", bitline_layer=None, strap_spacing=None, strap_layer="m2", tap_direction="row"):
self.cols = cols
self.route_layer = route_layer
self.strap_layer = strap_layer
self.tap_direction = tap_direction
if self.route_layer == "m1" :
if "li" in layer:
self.supply_layer = "li"
else:
self.supply_layer = "m1"
if bitline_layer is not None:
self.bitline_layer = bitline_layer
else:
self.bitline_layer = self.supply_layer
if name=="":
name = "rom_inv_array_{0}".format(cols)
@@ -65,17 +70,15 @@ class rom_precharge_array(design):
self.extend_well()
def add_boundary(self):
# self.translate_all(self.well_ll)
ur = self.find_highest_coords()
self.add_label(layer="nwell", text="upper right",offset=ur)
# ur = vector(ur.x, ur.y - self.well_ll.y)
super().add_boundary(vector(0, 0), ur)
self.height = ur.y
self.width = ur.x
def create_modules(self):
self.pmos = factory.create(module_type="rom_precharge_cell", module_name="precharge_cell", route_layer=self.route_layer, supply_layer=self.supply_layer)
self.pmos = factory.create(module_type="rom_precharge_cell", module_name="precharge_cell", bitline_layer=self.bitline_layer, supply_layer=self.supply_layer)
# For layout constants
self.dummy = factory.create(module_type="rom_base_cell")
@@ -115,7 +118,6 @@ class rom_precharge_array(design):
self.connect_inst([])
def place_instances(self):
self.add_label("ZERO", self.route_layer)
self.array_pos = []
strap_num = 0
@@ -145,7 +147,7 @@ class rom_precharge_array(design):
for col in range(self.cols):
source_pin = self.pmos_insts[col].get_pin("D")
bl = "pre_bl{0}_out".format(col)
self.add_layout_pin_rect_center(bl, self.route_layer, source_pin.center())
self.add_layout_pin_rect_center(bl, self.bitline_layer, source_pin.center())
def route_supply(self):
compiler/modules/rom_precharge_cell.py
+3 -3
View File
@@ -15,9 +15,9 @@ from openram.tech import drc
class rom_precharge_cell(rom_base_cell):
def __init__(self, name="", route_layer="m1", supply_layer="li"):
def __init__(self, name="", bitline_layer="m1", supply_layer="li"):
self.supply_layer = supply_layer
super().__init__(name=name, bitline_layer=route_layer)
super().__init__(name=name, bitline_layer=bitline_layer)
def create_layout(self):
super().create_layout()
@@ -74,7 +74,7 @@ class rom_precharge_cell(rom_base_cell):
from_layer=self.active_stack[2],
to_layer=self.supply_layer)
bitline_offset = vector( 2 * (drc("minwidth_{}".format(self.bitline_layer)) + drc("{0}_to_{0}".format(self.bitline_layer))) ,0)
bitline_offset = vector( 1.5 * (drc("minwidth_{}".format(self.bitline_layer)) + drc("{0}_to_{0}".format(self.bitline_layer))) ,0)
self.add_layout_pin_rect_center("vdd", self.supply_layer, pos - bitline_offset)