From 382c91f342a1ff366a9d6e72b069cf50c35a1a03 Mon Sep 17 00:00:00 2001 From: Jacob Walker Date: Wed, 1 Mar 2023 16:44:48 -0800 Subject: [PATCH] precharge array test passing sky130 --- compiler/modules/rom_base_array.py | 2 +- compiler/modules/rom_base_cell.py | 2 +- compiler/modules/rom_precharge_array.py | 18 ++++++++++-------- compiler/modules/rom_precharge_cell.py | 6 +++--- compiler/tests/05_rom_base_bank_small_test.py | 2 +- compiler/tests/05_rom_decoder_test.py | 2 +- compiler/tests/05_rom_precharge_array_test.py | 2 +- .../tests/05_rom_wordline_driver_array_test.py | 2 +- 8 files changed, 19 insertions(+), 17 deletions(-) diff --git a/compiler/modules/rom_base_array.py b/compiler/modules/rom_base_array.py index 99171450..dd4c80d4 100644 --- a/compiler/modules/rom_base_array.py +++ b/compiler/modules/rom_base_array.py @@ -89,7 +89,7 @@ class rom_base_array(bitcell_base_array): self.precharge_array = factory.create(module_type="rom_precharge_array", cols=self.column_size, strap_spacing=self.strap_spacing, - route_layer=self.bitline_layer, + bitline_layer=self.bitline_layer, strap_layer=self.wordline_layer, tap_direction=self.tap_direction) diff --git a/compiler/modules/rom_base_cell.py b/compiler/modules/rom_base_cell.py index 7663b420..28fc07f0 100644 --- a/compiler/modules/rom_base_cell.py +++ b/compiler/modules/rom_base_cell.py @@ -101,7 +101,7 @@ class rom_base_cell(design): # self.add_rect_center("poly", poly_offset, self.poly_extend_active_spacing, self.poly_width) self.cell_inst.place(tx_offset, rotate=90) - # self.add_label("CELL ZERO", self.route_layer) + self.copy_layout_pin(self.cell_inst, "S", "S") self.copy_layout_pin(self.cell_inst, "D", "D") self.source_pos = self.cell_inst.get_pin("S").center() diff --git a/compiler/modules/rom_precharge_array.py b/compiler/modules/rom_precharge_array.py index 8bd1b976..e034d402 100644 --- a/compiler/modules/rom_precharge_array.py +++ b/compiler/modules/rom_precharge_array.py @@ -17,17 +17,22 @@ class rom_precharge_array(design): """ An array of inverters to create the inverted address lines for the rom decoder """ - def __init__(self, cols, name="", route_layer="li", strap_spacing=None, strap_layer="m2", tap_direction="row"): + def __init__(self, cols, name="", bitline_layer=None, strap_spacing=None, strap_layer="m2", tap_direction="row"): self.cols = cols - self.route_layer = route_layer self.strap_layer = strap_layer self.tap_direction = tap_direction - if self.route_layer == "m1" : + if "li" in layer: self.supply_layer = "li" else: self.supply_layer = "m1" + if bitline_layer is not None: + self.bitline_layer = bitline_layer + else: + self.bitline_layer = self.supply_layer + + if name=="": name = "rom_inv_array_{0}".format(cols) @@ -65,17 +70,15 @@ class rom_precharge_array(design): self.extend_well() def add_boundary(self): - # self.translate_all(self.well_ll) ur = self.find_highest_coords() self.add_label(layer="nwell", text="upper right",offset=ur) - # ur = vector(ur.x, ur.y - self.well_ll.y) super().add_boundary(vector(0, 0), ur) self.height = ur.y self.width = ur.x def create_modules(self): - self.pmos = factory.create(module_type="rom_precharge_cell", module_name="precharge_cell", route_layer=self.route_layer, supply_layer=self.supply_layer) + self.pmos = factory.create(module_type="rom_precharge_cell", module_name="precharge_cell", bitline_layer=self.bitline_layer, supply_layer=self.supply_layer) # For layout constants self.dummy = factory.create(module_type="rom_base_cell") @@ -115,7 +118,6 @@ class rom_precharge_array(design): self.connect_inst([]) def place_instances(self): - self.add_label("ZERO", self.route_layer) self.array_pos = [] strap_num = 0 @@ -145,7 +147,7 @@ class rom_precharge_array(design): for col in range(self.cols): source_pin = self.pmos_insts[col].get_pin("D") bl = "pre_bl{0}_out".format(col) - self.add_layout_pin_rect_center(bl, self.route_layer, source_pin.center()) + self.add_layout_pin_rect_center(bl, self.bitline_layer, source_pin.center()) def route_supply(self): diff --git a/compiler/modules/rom_precharge_cell.py b/compiler/modules/rom_precharge_cell.py index 4489ccc9..3d4730aa 100644 --- a/compiler/modules/rom_precharge_cell.py +++ b/compiler/modules/rom_precharge_cell.py @@ -15,9 +15,9 @@ from openram.tech import drc class rom_precharge_cell(rom_base_cell): - def __init__(self, name="", route_layer="m1", supply_layer="li"): + def __init__(self, name="", bitline_layer="m1", supply_layer="li"): self.supply_layer = supply_layer - super().__init__(name=name, bitline_layer=route_layer) + super().__init__(name=name, bitline_layer=bitline_layer) def create_layout(self): super().create_layout() @@ -74,7 +74,7 @@ class rom_precharge_cell(rom_base_cell): from_layer=self.active_stack[2], to_layer=self.supply_layer) - bitline_offset = vector( 2 * (drc("minwidth_{}".format(self.bitline_layer)) + drc("{0}_to_{0}".format(self.bitline_layer))) ,0) + bitline_offset = vector( 1.5 * (drc("minwidth_{}".format(self.bitline_layer)) + drc("{0}_to_{0}".format(self.bitline_layer))) ,0) self.add_layout_pin_rect_center("vdd", self.supply_layer, pos - bitline_offset) diff --git a/compiler/tests/05_rom_base_bank_small_test.py b/compiler/tests/05_rom_base_bank_small_test.py index dbda8b41..e752db77 100644 --- a/compiler/tests/05_rom_base_bank_small_test.py +++ b/compiler/tests/05_rom_base_bank_small_test.py @@ -21,7 +21,7 @@ class rom_bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - debug.info(1, "Testing 32 byte rom cell") + debug.info(1, "Testing 64 byte rom cell") test_data = "{0}/{1}/rom_data_64B".format(os.getenv("OPENRAM_HOME"), OPTS.rom_data_dir) a = factory.create(module_type="rom_base_bank", strap_spacing = 8, data_file = test_data, word_size = 1) diff --git a/compiler/tests/05_rom_decoder_test.py b/compiler/tests/05_rom_decoder_test.py index 0ecea5cf..d6e5d27a 100644 --- a/compiler/tests/05_rom_decoder_test.py +++ b/compiler/tests/05_rom_decoder_test.py @@ -25,7 +25,7 @@ class rom_decoder_test(openram_test): debug.info(2, "Testing 2x4 decoder for rom cell") - a = factory.create(module_type="rom_decoder", num_outputs=16, strap_spacing=4, cols=16) + a = factory.create(module_type="rom_decoder", num_outputs=16, strap_spacing=4, fanout=16) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/05_rom_precharge_array_test.py b/compiler/tests/05_rom_precharge_array_test.py index 1d067709..7d585e66 100644 --- a/compiler/tests/05_rom_precharge_array_test.py +++ b/compiler/tests/05_rom_precharge_array_test.py @@ -13,7 +13,7 @@ import sys, os import openram from openram import OPTS from openram.sram_factory import factory -import debug +from openram import debug class rom_precharge_test(openram_test): diff --git a/compiler/tests/05_rom_wordline_driver_array_test.py b/compiler/tests/05_rom_wordline_driver_array_test.py index f3175127..f3da0e75 100644 --- a/compiler/tests/05_rom_wordline_driver_array_test.py +++ b/compiler/tests/05_rom_wordline_driver_array_test.py @@ -24,7 +24,7 @@ class wordline_driver_array_test(openram_test): # check wordline driver for single port debug.info(2, "Checking driver") - tx = factory.create(module_type="rom_wordline_driver_array", rows=8, cols=32) + tx = factory.create(module_type="rom_wordline_driver_array", rows=8, fanout=32) self.local_check(tx) openram.end_openram()