mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-30 01:48:33 +02:00
fix s_en in stim
This commit is contained in:
@@ -286,7 +286,7 @@ class delay(simulation):
|
||||
enable_name = sa_mods[0].get_enable_name()
|
||||
sen_name = self.get_alias_in_path(paths, enable_name, sa_mods[0])
|
||||
if OPTS.use_pex:
|
||||
#get sense amp multi bank
|
||||
sen_name = sen_name.split('.')[-1]
|
||||
return sen_name
|
||||
|
||||
def get_bl_name(self, paths, port):
|
||||
|
||||
@@ -480,7 +480,7 @@ class sram_1bank(sram_base):
|
||||
debug.error("Signal={} not contained in control logic connections={}"\
|
||||
.format(sen_name, control_conns))
|
||||
if sen_name in self.pins:
|
||||
debug.error("Internal signal={} contained in port list. Name defined by the parent.")
|
||||
debug.error("Internal signal={} contained in port list. Name defined by the parent.")
|
||||
return "X{}.{}".format(sram_name, sen_name)
|
||||
|
||||
def get_cell_name(self, inst_name, row, col):
|
||||
|
||||
Reference in New Issue
Block a user