From 364842569a0dec098bdb51bd64dedfa630d6317e Mon Sep 17 00:00:00 2001 From: jcirimel Date: Thu, 16 Jan 2020 12:16:49 -0800 Subject: [PATCH] fix s_en in stim --- compiler/characterizer/delay.py | 2 +- compiler/sram/sram_1bank.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 60039f89..f53e91a6 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -286,7 +286,7 @@ class delay(simulation): enable_name = sa_mods[0].get_enable_name() sen_name = self.get_alias_in_path(paths, enable_name, sa_mods[0]) if OPTS.use_pex: - #get sense amp multi bank + sen_name = sen_name.split('.')[-1] return sen_name def get_bl_name(self, paths, port): diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index c07b43e5..a141765b 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -480,7 +480,7 @@ class sram_1bank(sram_base): debug.error("Signal={} not contained in control logic connections={}"\ .format(sen_name, control_conns)) if sen_name in self.pins: - debug.error("Internal signal={} contained in port list. Name defined by the parent.") + debug.error("Internal signal={} contained in port list. Name defined by the parent.") return "X{}.{}".format(sram_name, sen_name) def get_cell_name(self, inst_name, row, col):