From 3526a57864e17dd3565b4a086492b228298d168c Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Sat, 25 Jun 2022 12:38:07 -0700 Subject: [PATCH] don't route rbl to conrol logic --- compiler/modules/bank.py | 2 +- compiler/modules/sram_1bank.py | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 88d8abc7..4b5b3f57 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -124,7 +124,7 @@ class bank(design): for port in self.all_ports: self.route_bitlines(port) - self.route_rbl(port) + # self.route_rbl(port) self.route_port_address(port) self.route_column_address_lines(port) self.route_control_lines(port) diff --git a/compiler/modules/sram_1bank.py b/compiler/modules/sram_1bank.py index a26ea7e8..818923c1 100644 --- a/compiler/modules/sram_1bank.py +++ b/compiler/modules/sram_1bank.py @@ -553,7 +553,7 @@ class sram_1bank(sram_base): src_pin = self.control_logic_insts[port].get_pin(signal) dest_pin = self.bank_inst.get_pin(signal + "{}".format(port)) self.connect_vbus(src_pin, dest_pin) - + """ for port in self.all_ports: # Only input (besides pins) is the replica bitline src_pin = self.control_logic_insts[port].get_pin("rbl_bl") @@ -566,6 +566,7 @@ class sram_1bank(sram_base): self.add_via_stack_center(from_layer=dest_pin.layer, to_layer="m3", offset=dest_pin.center()) + """ def route_row_addr_dff(self): """