diff --git a/compiler/base/design.py b/compiler/base/design.py
index c2ef8340..73ace38e 100644
--- a/compiler/base/design.py
+++ b/compiler/base/design.py
@@ -74,7 +74,7 @@ class design(hierarchy_design):
         return pitch
         
     def setup_drc_constants(self):
-        """ 
+        """
         These are some DRC constants used in many places
         in the compiler.
         """
diff --git a/compiler/base/wire.py b/compiler/base/wire.py
index bf1daa6a..250f2d87 100644
--- a/compiler/base/wire.py
+++ b/compiler/base/wire.py
@@ -6,18 +6,18 @@
 # All rights reserved.
 #
 from tech import drc
-import debug
 from wire_path import wire_path
 from sram_factory import factory
 
+
 class wire(wire_path):
-    """ 
+    """
     Object metal wire; given the layer type
-    Add a wire of minimium metal width between a set of points. 
+    Add a wire of minimium metal width between a set of points.
     The points should be rectilinear to control the bend points. If
     not, it will always go down first.
     The points are the center of the wire.
-    The layer stack is the vertical, contact/via, and horizontal layers, respectively. 
+    The layer stack is the vertical, contact/via, and horizontal layers, respectively.
     """
     def __init__(self, obj, layer_stack, position_list):
         self.obj = obj
@@ -36,6 +36,7 @@ class wire(wire_path):
         # wires and wire_paths should not be offset to (0,0)
 
     def setup_layers(self):
+
         (horiz_layer, via_layer, vert_layer) = self.layer_stack
         self.via_layer_name = via_layer
 
@@ -47,8 +48,16 @@ class wire(wire_path):
         via_connect = factory.create(module_type="contact",
                                      layer_stack=self.layer_stack,
                                      dimensions=(1, 1))
+
+        # This is used for short connections to avoid via-to-via spacing errors
+        self.vert_layer_contact_width = max(via_connect.second_layer_width,
+                                            via_connect.first_layer_width)
+        self.horiz_layer_contact_width = max(via_connect.second_layer_height,
+                                             via_connect.first_layer_height)
+        
         self.node_to_node = [drc("minwidth_" + str(self.horiz_layer_name)) + via_connect.width,
                              drc("minwidth_" + str(self.horiz_layer_name)) + via_connect.height]
+        self.pitch = max(self.node_to_node)
 
     # create a 1x1 contact
     def create_vias(self):
@@ -56,12 +65,9 @@ class wire(wire_path):
         self.c=factory.create(module_type="contact",
                               layer_stack=self.layer_stack,
                               dimensions=(1, 1))
-        c_width = self.c.width
-        c_height = self.c.height
-        
-        from itertools import tee,islice
-        nwise = lambda g,n=2: zip(*(islice(g,i,None) for i,g in enumerate(tee(g,n))))
-        threewise=nwise(self.position_list,3)
+        from itertools import tee, islice
+        nwise = lambda g, n=2: zip(*(islice(g, i, None) for i, g in enumerate(tee(g, n))))
+        threewise = nwise(self.position_list, 3)
 
         for (a, offset, c) in list(threewise):
             # add a exceptions to prevent a via when we don't change directions
@@ -72,18 +78,23 @@ class wire(wire_path):
             self.obj.add_via_center(layers=self.layer_stack,
                                     offset=offset)
 
-
     def create_rectangles(self):
-        """ 
+        """
         Create the actual rectangles on the appropriate layers
-        using the position list of the corners. 
+        using the position list of the corners.
         """
         pl = self.position_list  # position list
         for index in range(len(pl) - 1):
+            # Horizontal wire segment
             if pl[index][0] != pl[index + 1][0]:
                 line_length = pl[index + 1][0] - pl[index][0]
+                if abs(line_length) < self.pitch:
+                    width = self.horiz_layer_contact_width
+                else:
+                    width = self.horiz_layer_width
                 temp_offset = [pl[index][0],
-                               pl[index][1] - 0.5*self.horiz_layer_width]
+                               pl[index][1] - 0.5 * width]
+                # If we go in the negative direction, move the offset
                 if line_length < 0:
                     temp_offset = [temp_offset[0] + line_length,
                                    temp_offset[1]]
@@ -91,10 +102,15 @@ class wire(wire_path):
                               length=abs(line_length),
                               offset=temp_offset,
                               orientation="horizontal",
-                              layer_width=self.horiz_layer_width)
+                              layer_width=width)
+            # Vertical wire segment
             elif pl[index][1] != pl[index + 1][1]:
                 line_length = pl[index + 1][1] - pl[index][1]
-                temp_offset = [pl[index][0] - 0.5 * self.vert_layer_width,
+                if abs(line_length) < self.pitch:
+                    width = self.vert_layer_contact_width
+                else:
+                    width = self.vert_layer_width
+                temp_offset = [pl[index][0] - 0.5 * width,
                                pl[index][1]]
                 if line_length < 0:
                     temp_offset = [temp_offset[0],
@@ -103,11 +119,13 @@ class wire(wire_path):
                               length=abs(line_length),
                               offset=temp_offset,
                               orientation="vertical",
-                              layer_width=self.vert_layer_width)
+                              layer_width=width)
 
     def assert_node(self, A, B):
-        """ Check if the node movements are not big enough for the
-        technology sizes."""
+        """
+        Check if the node movements are not big enough for the
+        technology sizes.
+        """
         X_diff = abs(A[0] - B[0])
         Y_diff = abs(A[1] - B[1])
         [minX, minY] = self.node_to_node
diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py
index a805e635..f46849c6 100644
--- a/compiler/modules/hierarchical_decoder.py
+++ b/compiler/modules/hierarchical_decoder.py
@@ -33,7 +33,6 @@ class hierarchical_decoder(design.design):
         except AttributeError:
             self.cell_multiple = 1
         # For debugging
-        # self.cell_multiple = 2
         self.cell_height = self.cell_multiple * b.height
         
         self.num_outputs = num_outputs