diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py
index 99171875..d3dcffac 100644
--- a/compiler/modules/replica_bitcell_array.py
+++ b/compiler/modules/replica_bitcell_array.py
@@ -87,7 +87,7 @@ class replica_bitcell_array(bitcell_base_array):
             if port in self.left_rbl:
                 # These go top down starting from the bottom of the bitcell array.
                 replica_bit = self.rbl[0] - port - 1
-                column_offset = len(self.left_rbl)
+                column_offset = 0
             elif port in self.right_rbl:
                 # These go bottom up starting from the top of the bitcell array.
                 replica_bit = self.rbl[0] + self.row_size + port - 1
diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py
index 1645442e..37eebc2d 100644
--- a/compiler/modules/replica_column.py
+++ b/compiler/modules/replica_column.py
@@ -104,7 +104,16 @@ class replica_column(bitcell_base_array):
                     core_block[row][0] = geometry.instance("rbc_{}".format(row), mod=self.dummy_cell, is_bitcell=True)
                 else:
                     core_block[row][0] = geometry.instance("rbc_{}".format(row), mod=self.dummy_cell, is_bitcell=True, mirror='MX')
+
             current_row += 1
+        if self.cell.mirror.y:
+            print(self.column_offset)
+            for row in range(self.total_size):
+                if self.column_offset % 2 == 0:
+                    if core_block[row][0].mirror=='MX':
+                        core_block[row][0].mirror='XY'
+                    else:
+                        core_block[row][0].mirror='MY'
         self.pattern = pattern(self, "bitcell_array", core_block, num_rows=self.total_size, num_cols=self.column_size, name_template="rbc_r{0}_c{1}")
         self.pattern.connect_array()