luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-04 08:44:12 +02:00
Code Issues Packages Projects Releases Wiki Activity

Get rid of netgen error of undefined dlatch. Fix sp_read to find correct subckt name and pins.

Browse Source
This commit is contained in:
Matt Guthaus
2018-02-27 08:59:46 -08:00
parent 01244347c1
commit 2b839d34a3
3 changed files with 12 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/base/hierarchy_spice.py
+2 -2
View File
@@ -97,8 +97,8 @@ class spice(verilog.verilog):
for i in range(len(self.spice)):
self.spice[i] = self.spice[i].rstrip(" \n")
# find first subckt line in the file
subckt = re.compile("^.subckt", re.IGNORECASE)
# find the correct subckt line in the file
subckt = re.compile("^.subckt {}".format(self.name), re.IGNORECASE)
subckt_line = filter(subckt.search, self.spice)[0]
# parses line into ports and remove subckt
self.pins = subckt_line.split(" ")[2:]