diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py
index d218227e..1b722bd0 100644
--- a/compiler/base/hierarchy_spice.py
+++ b/compiler/base/hierarchy_spice.py
@@ -97,8 +97,8 @@ class spice(verilog.verilog):
             for i in range(len(self.spice)):
                 self.spice[i] = self.spice[i].rstrip(" \n")
 
-            # find first subckt line in the file
-            subckt = re.compile("^.subckt", re.IGNORECASE)
+            # find the correct subckt line in the file
+            subckt = re.compile("^.subckt {}".format(self.name), re.IGNORECASE)
             subckt_line = filter(subckt.search, self.spice)[0]
             # parses line into ports and remove subckt
             self.pins = subckt_line.split(" ")[2:]
diff --git a/technology/freepdk45/sp_lib/ms_flop.sp b/technology/freepdk45/sp_lib/ms_flop.sp
index e1967d84..03016e5d 100644
--- a/technology/freepdk45/sp_lib/ms_flop.sp
+++ b/technology/freepdk45/sp_lib/ms_flop.sp
@@ -1,10 +1,5 @@
 *master-slave flip-flop with both output and inverted ouput
 
-.SUBCKT ms_flop din dout dout_bar clk vdd gnd 
-xmaster din mout mout_bar clk clk_bar vdd gnd dlatch
-xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch
-.ENDS flop
-
 .SUBCKT dlatch din dout dout_bar clk clk_bar vdd gnd
 *clk inverter
 mPff1 clk_bar clk vdd vdd PMOS_VTG W=180.0n L=50n m=1
@@ -27,3 +22,8 @@ mtmP2 int1 clk_bar dout vdd PMOS_VTG W=180.0n L=50n m=1
 mtmN2 int1 clk dout gnd NMOS_VTG W=90n L=50n m=1
 .ENDS dlatch
 
+.SUBCKT ms_flop din dout dout_bar clk vdd gnd 
+xmaster din mout mout_bar clk clk_bar vdd gnd dlatch
+xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch
+.ENDS flop
+
diff --git a/technology/scn3me_subm/sp_lib/ms_flop.sp b/technology/scn3me_subm/sp_lib/ms_flop.sp
index 4cdf309f..abf664e7 100644
--- a/technology/scn3me_subm/sp_lib/ms_flop.sp
+++ b/technology/scn3me_subm/sp_lib/ms_flop.sp
@@ -1,10 +1,5 @@
 *master-slave flip-flop with both output and inverted ouput
 
-.subckt ms_flop din dout dout_bar clk vdd gnd 
-xmaster din mout mout_bar clk clk_bar vdd gnd dlatch
-xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch
-.ends flop
-
 .subckt dlatch din dout dout_bar clk clk_bar vdd gnd
 *clk inverter
 mPff1 clk_bar clk vdd vdd p W=1.8u L=0.6u m=1
@@ -27,3 +22,8 @@ mtmP2 int1 clk_bar dout vdd p W=1.8u L=0.6u m=1
 mtmN2 int1 clk dout gnd n W=0.9u L=0.6u m=1
 .ends dlatch
 
+.subckt ms_flop din dout dout_bar clk vdd gnd 
+xmaster din mout mout_bar clk clk_bar vdd gnd dlatch
+xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch
+.ends flop
+