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OpenRAM
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netlist_only done

This commit is contained in:
jcirimel 2020-02-09 23:51:01 -08:00
parent 7038fad930
commit 27eced1fbe
3 changed files with 11 additions and 6 deletions
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5
compiler/bitcells/bitcell.py
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@ -25,11 +25,12 @@ class bitcell(bitcell_base.bitcell_base):
if cell_properties.bitcell.split_wl: if cell_properties.bitcell.split_wl:
pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"] pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"]
else: else:
pin_names = ["bl", "br", "wl", "vdd", "gnd"] pin_names = ["bl", "br", "wl", "vdd", "gnd"]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
storage_nets = ['Q', 'Qbar'] storage_nets = ['Q', 'Qbar']
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
(width, height) = utils.get_libcell_size("cell_6t", (width, height) = utils.get_libcell_size("cell_6t",
GDS["unit"], GDS["unit"],
layer["boundary"]) layer["boundary"])

4
compiler/bitcells/replica_bitcell.py
View File

@ -20,10 +20,10 @@ class replica_bitcell(design.design):
if cell_properties.bitcell.split_wl: if cell_properties.bitcell.split_wl:
pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"] pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT" , "POWER", "GROUND"]
else: else:
pin_names = ["bl", "br", "wl", "vdd", "gnd"] pin_names = ["bl", "br", "wl", "vdd", "gnd"]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
if not OPTS.netlist_only: if not OPTS.netlist_only:
(width,height) = utils.get_libcell_size("replica_cell_6t", GDS["unit"], layer["boundary"]) (width,height) = utils.get_libcell_size("replica_cell_6t", GDS["unit"], layer["boundary"])

8
compiler/modules/control_logic.py
View File

@ -7,7 +7,7 @@
# #
from math import log from math import log
import design import design
from tech import drc, parameter from tech import drc, parameter, module_properties
import debug import debug
import contact import contact
from sram_factory import factory from sram_factory import factory
@ -742,7 +742,11 @@ class control_logic(design.design):
def create_dffs(self): def create_dffs(self):
self.ctrl_dff_inst=self.add_inst(name="ctrl_dffs", self.ctrl_dff_inst=self.add_inst(name="ctrl_dffs",
mod=self.ctrl_dff_array) mod=self.ctrl_dff_array)
self.connect_inst(self.input_list + self.dff_output_list + ["clk_buf"] + self.supply_list) inst_pins = self.input_list + self.dff_output_list + ["clk_buf"] + self.supply_list
if module_properties.dff_buff_array.add_body_contacts:
inst_pins.append("vpb")
inst_pins.append("vnb")
self.connect_inst(inst_pins)
def place_dffs(self): def place_dffs(self):
self.ctrl_dff_inst.place(vector(0,0)) self.ctrl_dff_inst.place(vector(0,0))