From 27eced1fbe0729c764117379c992cae405d14ada Mon Sep 17 00:00:00 2001 From: jcirimel Date: Sun, 9 Feb 2020 23:51:01 -0800 Subject: [PATCH] netlist_only done --- compiler/bitcells/bitcell.py | 5 +++-- compiler/bitcells/replica_bitcell.py | 4 ++-- compiler/modules/control_logic.py | 8 ++++++-- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/compiler/bitcells/bitcell.py b/compiler/bitcells/bitcell.py index a2ae66bf..49fdf19f 100644 --- a/compiler/bitcells/bitcell.py +++ b/compiler/bitcells/bitcell.py @@ -25,11 +25,12 @@ class bitcell(bitcell_base.bitcell_base): if cell_properties.bitcell.split_wl: pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"] + type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"] else: pin_names = ["bl", "br", "wl", "vdd", "gnd"] - + type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] storage_nets = ['Q', 'Qbar'] - type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] + (width, height) = utils.get_libcell_size("cell_6t", GDS["unit"], layer["boundary"]) diff --git a/compiler/bitcells/replica_bitcell.py b/compiler/bitcells/replica_bitcell.py index e67ce118..a869e4b7 100644 --- a/compiler/bitcells/replica_bitcell.py +++ b/compiler/bitcells/replica_bitcell.py @@ -20,10 +20,10 @@ class replica_bitcell(design.design): if cell_properties.bitcell.split_wl: pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"] + type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT" , "POWER", "GROUND"] else: pin_names = ["bl", "br", "wl", "vdd", "gnd"] - - type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] + type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] if not OPTS.netlist_only: (width,height) = utils.get_libcell_size("replica_cell_6t", GDS["unit"], layer["boundary"]) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index dbb7c3b7..fa11e30b 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -7,7 +7,7 @@ # from math import log import design -from tech import drc, parameter +from tech import drc, parameter, module_properties import debug import contact from sram_factory import factory @@ -742,7 +742,11 @@ class control_logic(design.design): def create_dffs(self): self.ctrl_dff_inst=self.add_inst(name="ctrl_dffs", mod=self.ctrl_dff_array) - self.connect_inst(self.input_list + self.dff_output_list + ["clk_buf"] + self.supply_list) + inst_pins = self.input_list + self.dff_output_list + ["clk_buf"] + self.supply_list + if module_properties.dff_buff_array.add_body_contacts: + inst_pins.append("vpb") + inst_pins.append("vnb") + self.connect_inst(inst_pins) def place_dffs(self): self.ctrl_dff_inst.place(vector(0,0))