mirror of https://github.com/VLSIDA/OpenRAM.git
fix positional getters
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parent
8d6d8f2f8c
commit
2565305158
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@ -254,28 +254,30 @@ class capped_replica_bitcell_array(bitcell_base_array):
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self.DRC_LVS()
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self.DRC_LVS()
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def get_main_array_top(self):
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def get_main_array_top(self):
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return self.replica_bitcell_array_inst.by() + self.replica_bitcell_array_inst.get_main_array_top()
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return self.replica_bitcell_array_inst.by() + self.replica_bitcell_array.get_main_array_top()
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def get_main_array_bottom(self):
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def get_main_array_bottom(self):
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return self.replica_bitcell_array_inst.by() + self.replica_bitcell_array_inst.get_main_array_bottom()
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return self.replica_bitcell_array_inst.by() + self.replica_bitcell_array.get_main_array_bottom()
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def get_main_array_left(self):
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def get_main_array_left(self):
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return self.replica_bitcell_array_inst.lx() + self.replica_bitcell_array_inst.get_main_array_left()
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return self.replica_bitcell_array_inst.lx() + self.replica_bitcell_array.get_main_array_left()
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def get_main_array_right(self):
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def get_main_array_right(self):
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return self.replica_bitcell_array_inst.lx() + self.replica_bitcell_array_inst.get_main_array_right()
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return self.replica_bitcell_array_inst.lx() + self.replica_bitcell_array.get_main_array_right()
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# FIXME: these names need to be changed to reflect what they're actually returning
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def get_replica_top(self):
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def get_replica_top(self):
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return self.replica_bitcell_array_inst.by() + self.replica_bitcell_array_inst.get_replica_top()
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return self.dummy_row_insts[1].by()
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def get_replica_bottom(self):
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def get_replica_bottom(self):
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return self.replica_bitcell_array_inst.by() + self.replica_bitcell_array_inst.get_replica_bottom()
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return self.dummy_row_insts[0].uy()
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def get_replica_left(self):
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def get_replica_left(self):
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return self.replica_bitcell_array_inst.lx() + self.replica_bitcell_array_inst.get_replica_left()
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return self.dummy_col_insts[0].lx()
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def get_replica_right(self):
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def get_replica_right(self):
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return self.replica_bitcell_array_inst.lx() + self.replica_bitcell_array_inst.get_replica_right()
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return self.dummy_col_insts[1].rx()
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def get_column_offsets(self):
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def get_column_offsets(self):
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"""
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"""
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@ -279,22 +279,6 @@ class replica_bitcell_array(bitcell_base_array):
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""" Return the right of the main bitcell array. """
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""" Return the right of the main bitcell array. """
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return self.bitcell_array_inst.rx()
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return self.bitcell_array_inst.rx()
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def get_replica_top(self):
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""" Return the top of all replica columns. """
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return self.dummy_row_insts[1].by()
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def get_replica_bottom(self):
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""" Return the bottom of all replica columns. """
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return self.dummy_row_insts[0].uy()
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def get_replica_left(self):
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""" Return the left of all replica columns. """
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return self.dummy_col_insts[0].lx()
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def get_replica_right(self):
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""" Return the right of all replica columns. """
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return self.dummy_col_insts[1].rx()
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def get_column_offsets(self):
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def get_column_offsets(self):
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"""
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"""
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Return an array of the x offsets of all the regular bits
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Return an array of the x offsets of all the regular bits
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