diff --git a/compiler/modules/capped_replica_bitcell_array.py b/compiler/modules/capped_replica_bitcell_array.py
index def4ab2a..d1f5d005 100644
--- a/compiler/modules/capped_replica_bitcell_array.py
+++ b/compiler/modules/capped_replica_bitcell_array.py
@@ -254,28 +254,30 @@ class capped_replica_bitcell_array(bitcell_base_array):
         self.DRC_LVS()
 
     def get_main_array_top(self):
-        return self.replica_bitcell_array_inst.by() + self.replica_bitcell_array_inst.get_main_array_top()
+        return self.replica_bitcell_array_inst.by() + self.replica_bitcell_array.get_main_array_top()
 
     def get_main_array_bottom(self):
-        return self.replica_bitcell_array_inst.by() + self.replica_bitcell_array_inst.get_main_array_bottom()
+        return self.replica_bitcell_array_inst.by() + self.replica_bitcell_array.get_main_array_bottom()
 
     def get_main_array_left(self):
-        return self.replica_bitcell_array_inst.lx() + self.replica_bitcell_array_inst.get_main_array_left()
+        return self.replica_bitcell_array_inst.lx() + self.replica_bitcell_array.get_main_array_left()
 
     def get_main_array_right(self):
-        return self.replica_bitcell_array_inst.lx() + self.replica_bitcell_array_inst.get_main_array_right()
+        return self.replica_bitcell_array_inst.lx() + self.replica_bitcell_array.get_main_array_right()
 
+    # FIXME: these names need to be changed to reflect what they're actually returning
     def get_replica_top(self):
-        return self.replica_bitcell_array_inst.by() + self.replica_bitcell_array_inst.get_replica_top()
+        return self.dummy_row_insts[1].by()
 
     def get_replica_bottom(self):
-        return self.replica_bitcell_array_inst.by() + self.replica_bitcell_array_inst.get_replica_bottom()
+        return self.dummy_row_insts[0].uy()
 
     def get_replica_left(self):
-        return self.replica_bitcell_array_inst.lx() + self.replica_bitcell_array_inst.get_replica_left()
+        return self.dummy_col_insts[0].lx()
 
     def get_replica_right(self):
-        return self.replica_bitcell_array_inst.lx() + self.replica_bitcell_array_inst.get_replica_right()
+        return self.dummy_col_insts[1].rx()
+
 
     def get_column_offsets(self):
         """
diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py
index e10dcbd2..3a3dca4f 100644
--- a/compiler/modules/replica_bitcell_array.py
+++ b/compiler/modules/replica_bitcell_array.py
@@ -279,22 +279,6 @@ class replica_bitcell_array(bitcell_base_array):
         """ Return the right of the main bitcell array. """
         return self.bitcell_array_inst.rx()
 
-    def get_replica_top(self):
-        """ Return the top of all replica columns. """
-        return self.dummy_row_insts[1].by()
-
-    def get_replica_bottom(self):
-        """ Return the bottom of all replica columns. """
-        return self.dummy_row_insts[0].uy()
-
-    def get_replica_left(self):
-        """ Return the left of all replica columns. """
-        return self.dummy_col_insts[0].lx()
-
-    def get_replica_right(self):
-        """ Return the right of all replica columns. """
-        return self.dummy_col_insts[1].rx()
-
     def get_column_offsets(self):
         """
         Return an array of the x offsets of all the regular bits