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fix indentation errors, typos, and missing iterator

This commit is contained in:
samuelkcrow 2022-06-25 15:14:46 -07:00
parent 3526a57864
commit 1e1ec54275
2 changed files with 8 additions and 6 deletions
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7
compiler/modules/control_logic_delay.py
View File

@ -368,6 +368,7 @@ class control_logic_delay(design.design):
self.route_sen() self.route_sen()
self.route_delay() self.route_delay()
self.route_pen() self.route_pen()
self.route_glitches()
self.route_clk_buf() self.route_clk_buf()
self.route_gated_clk_bar() self.route_gated_clk_bar()
self.route_gated_clk_buf() self.route_gated_clk_buf()
@ -391,10 +392,10 @@ class control_logic_delay(design.design):
self.delay_inst.place(offset, mirror="MX") self.delay_inst.place(offset, mirror="MX")
def route_delay(self): def route_delay(self):
delay_map = zip(["in", "delay1", "delay2", "delay3", "delay4", "delay5"], delay_map = zip(["in", "delay1", "delay2", "delay3", "delay4", "delay5"], \
["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "delay5"]) ["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "delay5"])
slef.connect_vertical_bus(delay_map, self.delay_inst, self.input_bus) self.connect_vertical_bus(delay_map, self.delay_inst, self.input_bus)
# glitch{1-3} are internal timing signals based on different in/out # glitch{1-3} are internal timing signals based on different in/out
# points on the delay chain for adjustable start time and duration # points on the delay chain for adjustable start time and duration
@ -646,7 +647,7 @@ class control_logic_delay(design.design):
def place_wen_row(self, row): def place_wen_row(self, row):
x_offset = self.control_x_offset x_offset = self.control_x_offset
x_offset = self.place_util(self.glitch3_bar_inv_inst, x_offset, row) x_offset = self.place_util(self.glitch3_bar_inv_inst, x_offset, row)
x_offset = self.place_util(self.w_en_gate_inst, x_offset, row) x_offset = self.place_util(self.w_en_gate_inst, x_offset, row)
self.row_end_inst.append(self.w_en_gate_inst) self.row_end_inst.append(self.w_en_gate_inst)

7
compiler/modules/multi_delay_chain.py
View File

@ -217,10 +217,10 @@ class multi_delay_chain(design.design):
layer="m2", layer="m2",
offset=mid_loc) offset=mid_loc)
delay_number = 1 delay_number = 1
for pin_number in pinout_list: for pin_number in self.pinout_list:
# output is A pin of last load/fanout inverter # output is A pin of last load/fanout inverter
output_driver_inst = self.driver_inst_list[pin_number] output_driver_inst = self.driver_inst_list[pin_number - 1]
a_pin = self.load_inst_map[output_driver_inst][-1].get_pin("A") a_pin = self.load_inst_map[output_driver_inst][-1].get_pin("A")
self.add_via_stack_center(from_layer=a_pin.layer, self.add_via_stack_center(from_layer=a_pin.layer,
to_layer="m1", to_layer="m1",
@ -228,3 +228,4 @@ class multi_delay_chain(design.design):
self.add_layout_pin_rect_center(text="delay{}".format(str(delay_number)), self.add_layout_pin_rect_center(text="delay{}".format(str(delay_number)),
layer="m1", layer="m1",
offset=a_pin.center()) offset=a_pin.center())
delay_number += 1