From 1aa04db2b601fc714e5b0ba9a87af2741e5f1509 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Thu, 3 Aug 2023 16:24:24 -0700 Subject: [PATCH] add isntance naming templates --- compiler/characterizer/simulation.py | 4 ++++ compiler/modules/bitcell_array.py | 8 ++++---- compiler/modules/dummy_array.py | 6 +++--- compiler/modules/pattern.py | 4 +++- compiler/modules/replica_column.py | 2 +- 5 files changed, 15 insertions(+), 9 deletions(-) diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index c49f0e63..3ef33d10 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -619,6 +619,10 @@ class simulation(): bl_names = [] exclude_set = self.get_bl_name_search_exclusions() + print(paths) + print(cell_bl) + print(cell_mod) + print(exclude_set) for int_net in [cell_bl, cell_br]: bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set)) if OPTS.use_pex and OPTS.pex_exe[0] != "calibre": diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index b05cfd23..319691ba 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -64,12 +64,12 @@ class bitcell_array(bitcell_base_array): core_block[0][0] = geometry.instance("core_0_0", mod=self.cell, is_bitcell=True) core_block[1][0] = geometry.instance("core_1_0", mod=self.cell, is_bitcell=True, mirror='MX') - self.pattern = pattern(self, "bitcell_array", core_block, num_rows=self.row_size, num_cols=self.column_size) + self.pattern = pattern(self, "bitcell_array", core_block, num_rows=self.row_size, num_cols=self.column_size,name_template="bit_r{0}_c{1}") self.pattern.connect_array() - for key in self.cell_inst.keys(): - if key != (0,0): - self.trim_insts.add(self.cell_inst[key].name) + #for key in self.cell_inst.keys(): + # if key != (0,0): + # self.trim_insts.add(self.cell_inst[key].name) def analytical_power(self, corner, load): """Power of Bitcell array and bitline in nW.""" diff --git a/compiler/modules/dummy_array.py b/compiler/modules/dummy_array.py index a8ec957b..ced3de20 100644 --- a/compiler/modules/dummy_array.py +++ b/compiler/modules/dummy_array.py @@ -53,11 +53,11 @@ class dummy_array(bitcell_base_array): """ Create the module instances used in this design """ self.cell_inst={} core_block = [[0 for x in range(1)] for y in range(2)] - core_block[0][(0+self.mirror) %2] = geometry.instance("core_0_0", mod=self.dummy_cell, is_bitcell=True) - core_block[0][(1+self.mirror) %2] = geometry.instance("core_1_0", mod=self.dummy_cell, is_bitcell=True, mirror='MX') + core_block[(0+self.mirror) %2][0] = geometry.instance("core_0_0", mod=self.dummy_cell, is_bitcell=True) + core_block[(1+self.mirror) %2][0] = geometry.instance("core_1_0", mod=self.dummy_cell, is_bitcell=True, mirror='MX') - self.pattern = pattern(self, "dummy_array", core_block, num_rows=self.row_size, num_cols=self.column_size) + self.pattern = pattern(self, "dummy_array", core_block, num_rows=self.row_size, num_cols=self.column_size, name_template="bit_r{0}_c{1}") self.pattern.connect_array() diff --git a/compiler/modules/pattern.py b/compiler/modules/pattern.py index 00c21783..feb04927 100644 --- a/compiler/modules/pattern.py +++ b/compiler/modules/pattern.py @@ -23,6 +23,7 @@ class pattern(): core_block:block, num_rows:int, num_cols:int, + name_template, num_cores_x: Optional[int] = 0, num_cores_y: Optional[int] = 0, cores_per_x_block: int = 1, @@ -50,6 +51,7 @@ class pattern(): self.core_block = core_block self.num_rows = num_rows self.num_cols = num_cols + self.name_template = name_template self.num_cores_x = num_cores_x self.num_cores_y = num_cores_y if num_cores_x == 0: @@ -122,7 +124,7 @@ class pattern(): if(inst.is_bitcell): self.bit_rows[col+dc] += 1 self.bit_cols[row+dr] += 1 - self.parent_design.cell_inst[row + dr, col + dc] = self.parent_design.add_existing_inst(inst,"bit_r{}_c{}".format(row +dr, col+dc)) + self.parent_design.cell_inst[row + dr, col + dc] = self.parent_design.add_existing_inst(inst,self.name_template.format(row +dr, col+dc)) self.parent_design.connect_inst(self.parent_design.get_bitcell_pins(row+dr, col+dc)) def connect_array(self) -> None: diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index 944b9b94..84f8f1c6 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -105,7 +105,7 @@ class replica_column(bitcell_base_array): else: core_block[row][0] = geometry.instance("rbc_{}".format(row), mod=self.dummy_cell, is_bitcell=True) current_row += 1 - self.pattern = pattern(self, "bitcell_array", core_block, num_rows=self.total_size, num_cols=self.column_size) + self.pattern = pattern(self, "bitcell_array", core_block, num_rows=self.total_size, num_cols=self.column_size, name_template="rbc_r{0}_c{1}") self.pattern.connect_array() def add_layout_pins(self):