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https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-05 01:01:33 +02:00
syncronize bitline naming convention betwen bitcell and pbitcell
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@@ -417,11 +417,11 @@ def correct_port(name, output_file_name, ref_file_name):
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for bank in range(OPTS.num_banks):
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for row in range(OPTS.num_words):
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for col in range(OPTS.word_size):
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bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row,col)
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bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row,col)
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bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row, col)
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bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row, col)
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for col in range(OPTS.word_size):
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bitcell_list += "bl{0}_{2} ".format(bank, row,col)
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bitcell_list += "br{0}_{2} ".format(bank, row,col)
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bitcell_list += "bl{0}_{2} ".format(bank, row, col)
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bitcell_list += "br{0}_{2} ".format(bank, row, col)
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bitcell_list += "\n"
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control_list = "+ "
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