From 1a97dfc63e29b52db7ebf579c1c1c2eefaea97c0 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Mon, 27 Jan 2020 11:50:43 +0000 Subject: [PATCH] syncronize bitline naming convention betwen bitcell and pbitcell --- compiler/characterizer/delay.py | 37 ++++++++++++++++++++----------- compiler/characterizer/stimuli.py | 5 +++-- compiler/sram/sram_base.py | 11 +++------ compiler/verify/magic.py | 8 +++---- 4 files changed, 34 insertions(+), 27 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 6ec3ae8a..36965f4d 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -130,19 +130,18 @@ class delay(simulation): """ self.bitline_volt_meas = [] - self.bitline_volt_meas.append(voltage_at_measure("v_bl_READ_ZERO", - self.bl_name)) + self.bl_name)) self.bitline_volt_meas[-1].meta_str = sram_op.READ_ZERO self.bitline_volt_meas.append(voltage_at_measure("v_br_READ_ZERO", - self.br_name)) + self.br_name)) self.bitline_volt_meas[-1].meta_str = sram_op.READ_ZERO self.bitline_volt_meas.append(voltage_at_measure("v_bl_READ_ONE", - self.bl_name)) + self.bl_name)) self.bitline_volt_meas[-1].meta_str = sram_op.READ_ONE self.bitline_volt_meas.append(voltage_at_measure("v_br_READ_ONE", - self.br_name)) + self.br_name)) self.bitline_volt_meas[-1].meta_str = sram_op.READ_ONE return self.bitline_volt_meas @@ -264,14 +263,26 @@ class delay(simulation): """Sets important names for characterization such as Sense amp enable and internal bit nets.""" port = self.read_ports[0] - self.graph.get_all_paths('{}{}'.format("clk", port), - '{}{}_{}'.format(self.dout_name, port, self.probe_data)) - - self.sen_name = self.get_sen_name(self.graph.all_paths) - debug.info(2,"s_en name = {}".format(self.sen_name)) - - self.bl_name,self.br_name = self.get_bl_name(self.graph.all_paths, port) - debug.info(2,"bl name={}, br name={}".format(self.bl_name,self.br_name)) + if not OPTS.use_pex: + self.graph.get_all_paths('{}{}'.format("clk", port), + '{}{}_{}'.format(self.dout_name, port, self.probe_data)) + + self.sen_name = self.get_sen_name(self.graph.all_paths) + debug.info(2,"s_en name = {}".format(self.sen_name)) + + self.bl_name,self.br_name = self.get_bl_name(self.graph.all_paths, port) + debug.info(2,"bl name={}, br name={}".format(self.bl_name,self.br_name)) + else: + self.graph.get_all_paths('{}{}'.format("clk", port), + '{}{}_{}'.format(self.dout_name, port, self.probe_data)) + + self.sen_name = self.get_sen_name(self.graph.all_paths) + debug.info(2,"s_en name = {}".format(self.sen_name)) + + + self.bl_name = "bl{0}_{1}".format(port, OPTS.word_size-1) + self.br_name = "br{0}_{1}".format(port, OPTS.word_size-1) + debug.info(2,"bl name={}, br name={}".format(self.bl_name,self.br_name)) def get_sen_name(self, paths): """ diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index b4cd00f4..198dacdd 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -63,8 +63,9 @@ class stimuli(): self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col)) self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col)) for col in range(OPTS.word_size): - self.sf.write("bl{0}_{2} ".format(bank, row,col)) - self.sf.write("br{0}_{2} ".format(bank, row,col)) + self.sf.write("bl{0}_{2} ".format(bank, row, col)) + self.sf.write("br{0}_{2} ".format(bank, row, col)) + self.sf.write("s_en{0} ".format(bank)) self.sf.write("{0}\n".format(model_name)) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 2c66924a..3479957b 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -125,16 +125,11 @@ class sram_base(design, verilog, lef): br.append(bitline_location) for col in range(len(bl)): - if OPTS.num_banks == 1: - self.add_layout_pin_rect_center("bl0_{0}".format(int(col / OPTS.num_words)), bitline_layer_name, bl[col]) - else: - self.add_layout_pin_rect_center("bl{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl) + self.add_layout_pin_rect_center("bl{0}_{1}".format(bank_num, int(col / OPTS.num_words)), bitline_layer_name, bl[col]) for col in range(len(br)): - if OPTS.num_banks == 1: - self.add_layout_pin_rect_center("br0_{0}".format(int(col / OPTS.num_words)), bitline_layer_name, br[col]) - else: - self.add_layout_pin_rect_center("br{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, br) + self.add_layout_pin_rect_center("br{0}_{1}".format(bank_num, int(col / OPTS.num_words)), bitline_layer_name, br[col]) + diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index d81255b6..93472e2a 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -417,11 +417,11 @@ def correct_port(name, output_file_name, ref_file_name): for bank in range(OPTS.num_banks): for row in range(OPTS.num_words): for col in range(OPTS.word_size): - bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row,col) - bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row,col) + bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row, col) + bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row, col) for col in range(OPTS.word_size): - bitcell_list += "bl{0}_{2} ".format(bank, row,col) - bitcell_list += "br{0}_{2} ".format(bank, row,col) + bitcell_list += "bl{0}_{2} ".format(bank, row, col) + bitcell_list += "br{0}_{2} ".format(bank, row, col) bitcell_list += "\n" control_list = "+ "