luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-07 02:58:49 +02:00
Code Issues Packages Projects Releases Wiki Activity

syncronize bitline naming convention betwen bitcell and pbitcell

Browse Source
This commit is contained in:
Jesse Cirimelli-Low
2020-01-27 11:50:43 +00:00
parent d42cd9a281
commit 1a97dfc63e
4 changed files with 34 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/sram/sram_base.py
+3 -8
View File
@@ -125,16 +125,11 @@ class sram_base(design, verilog, lef):
br.append(bitline_location)
for col in range(len(bl)):
if OPTS.num_banks == 1:
self.add_layout_pin_rect_center("bl0_{0}".format(int(col / OPTS.num_words)), bitline_layer_name, bl[col])
else:
self.add_layout_pin_rect_center("bl{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl)
self.add_layout_pin_rect_center("bl{0}_{1}".format(bank_num, int(col / OPTS.num_words)), bitline_layer_name, bl[col])
for col in range(len(br)):
if OPTS.num_banks == 1:
self.add_layout_pin_rect_center("br0_{0}".format(int(col / OPTS.num_words)), bitline_layer_name, br[col])
else:
self.add_layout_pin_rect_center("br{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, br)
self.add_layout_pin_rect_center("br{0}_{1}".format(bank_num, int(col / OPTS.num_words)), bitline_layer_name, br[col])