luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 09:58:33 +02:00
Code Issues Packages Projects Releases Wiki Activity

Changing control logic names to match naming scheme for multi-port. din[0] to din0[0], s_en to s_en0, addr[0] to addr0[0], etc. Sram level should pass unit tests for single port but will not currently pass for multi-port

Browse Source
This commit is contained in:
Michael Timothy Grimes
2018-08-18 16:51:21 -07:00
parent 0f8da1510e
commit 19ca0d6c2a
4 changed files with 16 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/bank.py
+5 -6
View File
@@ -133,7 +133,6 @@ class bank(design.design):
self.add_row_decoder()
self.add_wordline_driver()
self.add_column_decoder()
def compute_sizes(self):
@@ -201,7 +200,7 @@ class bank(design.design):
self.precharge_array = [None] * self.total_read
for k in range(self.total_read):
self.precharge_array[k] = self.mod_precharge_array(columns=self.num_cols, BL=self.read_bl_list[k], BR=self.read_br_list[k])
self.precharge_array[k] = self.mod_precharge_array(columns=self.num_cols, bitcell_bl=self.read_bl_list[k], bitcell_br=self.read_br_list[k])
self.add_mod(self.precharge_array[k])
if self.col_addr_size > 0:
@@ -521,7 +520,7 @@ class bank(design.design):
#the column decoder (if there is one).
write_driver_min_y_offset = self.write_driver_array_inst[0].by() - 3*self.m2_pitch
row_decoder_min_y_offset = self.row_decoder_inst[0].by()
if self.col_addr_size > 0:
col_decoder_min_y_offset = self.col_decoder_inst[0].by()
else:
@@ -575,8 +574,8 @@ class bank(design.design):
for k in range(self.total_read):
for i in range(self.num_cols):
precharge_bl = self.precharge_array_inst[k].get_pin(self.read_bl_list[k]+"[{}]".format(i)).bc()
precharge_br = self.precharge_array_inst[k].get_pin(self.read_br_list[k]+"[{}]".format(i)).bc()
precharge_bl = self.precharge_array_inst[k].get_pin("bl[{}]".format(i)).bc()
precharge_br = self.precharge_array_inst[k].get_pin("br[{}]".format(i)).bc()
bitcell_bl = self.bitcell_array_inst.get_pin(self.read_bl_list[k]+"[{}]".format(i)).uc()
bitcell_br = self.bitcell_array_inst.get_pin(self.read_br_list[k]+"[{}]".format(i)).uc()
@@ -631,7 +630,7 @@ class bank(design.design):
self.add_path("metal2",[sense_amp_br, vector(sense_amp_br.x,yoffset),
vector(connect_br.x,yoffset), connect_br])
def route_sense_amp_out(self):
""" Add pins for the sense amp output """
for i in range(self.word_size):
compiler/modules/control_logic.py
+5 -5
View File
@@ -100,7 +100,7 @@ class control_logic(design.design):
# leave space for the bus plus one extra space
self.internal_bus_width = (len(self.internal_bus_list)+1)*self.m2_pitch
# Outputs to the bank
self.output_list = ["s_en", "w_en", "clk_buf_bar", "clk_buf"]
self.output_list = ["s_en0", "w_en0", "clk_buf_bar", "clk_buf"]
self.supply_list = ["vdd", "gnd"]
@@ -231,7 +231,7 @@ class control_logic(design.design):
mod=self.inv8,
offset=self.s_en_offset,
mirror=mirror)
self.connect_inst(["pre_s_en_bar", "s_en", "vdd", "gnd"])
self.connect_inst(["pre_s_en_bar", "s_en0", "vdd", "gnd"])
self.row_end_inst.append(self.s_en_inst)
@@ -313,7 +313,7 @@ class control_logic(design.design):
mod=self.inv8,
offset=w_en_offset,
mirror=mirror)
self.connect_inst(["pre_w_en_bar", "w_en", "vdd", "gnd"])
self.connect_inst(["pre_w_en_bar", "w_en0", "vdd", "gnd"])
x_off += self.inv8.width
self.row_end_inst.append(self.w_en_inst)
@@ -406,7 +406,7 @@ class control_logic(design.design):
self.add_path("metal1",[self.pre_w_en_inst.get_pin("Z").center(), self.pre_w_en_bar_inst.get_pin("A").center()])
self.add_path("metal1",[self.pre_w_en_bar_inst.get_pin("Z").center(), self.w_en_inst.get_pin("A").center()])
self.connect_output(self.w_en_inst, "Z", "w_en")
self.connect_output(self.w_en_inst, "Z", "w_en0")
def route_sen(self):
rbl_out_pos = self.rbl_inst.get_pin("out").bc()
@@ -417,7 +417,7 @@ class control_logic(design.design):
self.add_path("metal1",[self.pre_s_en_bar_inst.get_pin("Z").center(), self.s_en_inst.get_pin("A").center()])
self.connect_output(self.s_en_inst, "Z", "s_en")
self.connect_output(self.s_en_inst, "Z", "s_en0")
def route_clk(self):
""" Route the clk and clk_buf_bar signal internally """