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Merged with dev, conflict in golden data of hspice delay test.

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Hunter Nichols
2019-10-01 14:26:34 -07:00
parent 1bdd9f56d6 b0dcfb5b2d
commit 19a09470d4
7 changed files with 298 additions and 187 deletions
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compiler/tests/21_hspice_delay_test.py
+10 -10
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@@ -61,16 +61,16 @@ class timing_sram_test(openram_test):
data.update(port_data[0])
if OPTS.tech_name == "freepdk45":
golden_data = {'delay_hl': [0.2181231],
'delay_lh': [0.2181231],
'leakage_power': 0.0025453999999999997,
'min_period': 0.781,
'read0_power': [0.34664159999999994],
'read1_power': [0.32656349999999995],
'slew_hl': [0.21136519999999998],
'slew_lh': [0.21136519999999998],
'write0_power': [0.37980179999999997],
'write1_power': [0.3532026]}
golden_data = {'delay_hl': [0.2383338],
'delay_lh': [0.2383338],
'leakage_power': 0.0014532999999999998,
'min_period': 0.898,
'read0_power': [0.30059800000000003],
'read1_power': [0.30061810000000005],
'slew_hl': [0.25358420000000004],
'slew_lh': [0.25358420000000004],
'write0_power': [0.34616749999999996],
'write1_power': [0.2792924]}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {'delay_hl': [1.7445000000000002],
'delay_lh': [1.7445000000000002],