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Use spare rows only for sky130

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This commit is contained in:
mrg
2021-09-07 16:49:11 -07:00
parent 83f2d14646
commit 178f1197ca
2 changed files with 11 additions and 5 deletions
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compiler/tests/50_riscv_1rw_func_test.py
-1
View File
@@ -26,7 +26,6 @@ class riscv_func_test(openram_test):
OPTS.netlist_only = True
OPTS.trim_netlist = False
if OPTS.tech_name == "sky130":
num_spare_rows = 1
num_spare_cols = 1
compiler/tests/50_riscv_1rw_phys_test.py
+11 -4
View File
@@ -16,7 +16,7 @@ from sram_factory import factory
import debug
@unittest.skip("SKIPPING 50_riscv_phys_test")
#@unittest.skip("SKIPPING 50_riscv_phys_test")
class riscv_phys_test(openram_test):
def runTest(self):
@@ -24,6 +24,13 @@ class riscv_phys_test(openram_test):
globals.init_openram(config_file)
from sram_config import sram_config
if OPTS.tech_name == "sky130":
num_spare_rows = 1
num_spare_cols = 1
else:
num_spare_rows = 0
num_spare_cols = 0
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
@@ -36,9 +43,9 @@ class riscv_phys_test(openram_test):
write_size=8,
num_words=32,
num_banks=1,
num_spare_rows=1,
num_spare_cols=1)
c.words_per_row=2
num_spare_cols=num_spare_cols,
num_spare_rows=num_spare_rows)
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w sram "
"with {} bit words, {} words, {} words per "