diff --git a/compiler/tests/50_riscv_1rw_func_test.py b/compiler/tests/50_riscv_1rw_func_test.py
index 6f0b668d..0e7e79d7 100755
--- a/compiler/tests/50_riscv_1rw_func_test.py
+++ b/compiler/tests/50_riscv_1rw_func_test.py
@@ -26,7 +26,6 @@ class riscv_func_test(openram_test):
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
 
-
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1
diff --git a/compiler/tests/50_riscv_1rw_phys_test.py b/compiler/tests/50_riscv_1rw_phys_test.py
index 6d9ad843..4cf2def5 100755
--- a/compiler/tests/50_riscv_1rw_phys_test.py
+++ b/compiler/tests/50_riscv_1rw_phys_test.py
@@ -16,7 +16,7 @@ from sram_factory import factory
 import debug
 
 
-@unittest.skip("SKIPPING 50_riscv_phys_test")
+#@unittest.skip("SKIPPING 50_riscv_phys_test")
 class riscv_phys_test(openram_test):
 
     def runTest(self):
@@ -24,6 +24,13 @@ class riscv_phys_test(openram_test):
         globals.init_openram(config_file)
         from sram_config import sram_config
 
+        if OPTS.tech_name == "sky130":
+            num_spare_rows = 1
+            num_spare_cols = 1
+        else:
+            num_spare_rows = 0
+            num_spare_cols = 0
+
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
@@ -36,9 +43,9 @@ class riscv_phys_test(openram_test):
                         write_size=8,
                         num_words=32,
                         num_banks=1,
-                        num_spare_rows=1,
-                        num_spare_cols=1)
-        c.words_per_row=2
+                        num_spare_cols=num_spare_cols,
+                        num_spare_rows=num_spare_rows)
+        c.words_per_row=1
         c.recompute_sizes()
         debug.info(1, "Layout test for {}rw,{}r,{}w sram "
                    "with {} bit words, {} words, {} words per "