Added write_size to control_logic_r parameters.

2019-07-05 11:40:02 -07:00 · 2019-07-05 11:40:02 -07:00 · 150259e2ba
parent 02a0cd71ac
commit 150259e2ba
1 changed files with 1 additions and 0 deletions
--- a/compiler/sram/sram_base.py
+++ b/compiler/sram/sram_base.py
@ -324,6 +324,7 @@ class sram_base(design, verilog, lef):
            self.control_logic_r = self.mod_control_logic(num_rows=self.num_rows, 
                                                          words_per_row=self.words_per_row,
                                                          word_size=self.word_size,
+                                                          write_size=self.write_size,
                                                          sram=self,
                                                          port_type="r")
            self.add_mod(self.control_logic_r)